专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130187118A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20130187118A1
公开(公告)日：2013-07-25
申请号：US13357149
申请日：2012-01-24
申请人： Kenichi MUROOKA
发明人： Kenichi MUROOKA
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/249 , H01L23/5226 , H01L23/528 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/16
摘要： According to one embodiment, a memory device includes a first interconnect group, a second interconnect group, and a memory cell. In the first interconnect group, first interconnects are stacked. The first interconnect group includes first regions in which the first interconnects are formed along a first direction, and a second region in which first contact plugs are formed on the first interconnects. In the second region, the first interconnect group includes a step portion. Heights of adjacent terraces of the step portion are different from each other by the two or more first interconnects.
摘要翻译：根据一个实施例，存储器件包括第一互连组，第二互连组和存储单元。在第一互连组中，堆叠第一互连。第一互连组包括沿着第一方向形成第一互连的第一区域和在第一互连件上形成第一接触插塞的第二区域。在第二区域中，第一互连组包括台阶部分。阶梯部分的相邻台阶的高度通过两个或更多个第一互连彼此不同。

2. 发明申请

US20120182784A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120182784A1
公开(公告)日：2012-07-19
申请号：US13327065
申请日：2011-12-15
申请人： Kenichi MUROOKA
发明人： Kenichi MUROOKA
IPC分类号： G11C11/00
CPC分类号： H01L45/1233 , G11C8/10 , G11C13/0002 , G11C13/0023 , G11C2213/71 , G11C2213/72 , H01L27/2463 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1608
摘要： A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2
摘要翻译：根据一个实施例的半导体存储器件包括由多个行线和列线构成的存储单元阵列，所述多个行线和列线彼此相交，并且从布置在行线和列线的每个交点处的多个存储单元组成，并且每个包括可变电阻元件。在假设行数为N的情况下，假设列数为M，当存储单元中存在的一个存储单元中的电池电流为选择电压的一半时的电流比当将选择电压施加到一个存储器单元时，将存储单元中的一个施加到流过该存储单元中的一个存储单元的单元电流，则关系M2 <2×N×k 满意。

3. 发明申请

US20090068765A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法和制造半导体器件的装置
公开(公告)号：US20090068765A1
公开(公告)日：2009-03-12
申请号：US11969564
申请日：2008-01-04
申请人： Kenichi MUROOKA
发明人： Kenichi MUROOKA
IPC分类号： H01L21/02 , B32B37/14
CPC分类号： G03F9/703 , B82Y10/00 , B82Y40/00 , G03F7/0002 , G03F7/703 , G03F7/7035 , G03F9/7003 , G03F9/7038 , G03F9/7042 , H01L27/1469
摘要： A method of manufacturing a semiconductor device includes performing positioning between a transfer position of a pattern forming surface of a transfer original plate on which a pattern to be transferred is formed and a transferred position of a transferred surface of a transferred substrate to which the pattern is to be transferred; contacting the pattern forming surface with the transferred surface; and partly correcting the positional deviation between the transfer position of the pattern forming surface and the transferred position of the transferred surface in the in-plane direction, after the positioning is performed.
摘要翻译：一种制造半导体器件的方法包括：在其上形成有转印图案的转印原版的图案形成表面的转印位置与转印的基板的转印表面的转印位置之间进行定位，被转让使图案形成表面与转印表面接触; 并且在进行定位之后部分地校正图案形成表面的转印位置和转印表面在面内方向上的转印位置之间的位置偏差。

4. 发明申请

US20130010520A1 MEMORY DEVICE AND FABRICATING METHOD THEREOF 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20130010520A1
公开(公告)日：2013-01-10
申请号：US13177857
申请日：2011-07-07
申请人： Kenichi MUROOKA
发明人： Kenichi MUROOKA
IPC分类号： G11C11/21 , H01L45/00 , H01L21/8239
CPC分类号： H01L45/122 , G11C13/0002 , G11C2213/71 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/124 , H01L45/146 , H01L45/147 , H01L45/1691
摘要： According to one embodiment, a memory device includes first interconnects, second interconnects, and a first memory cell. The first memory cell is located in an intersection of one of the first interconnects and one of the second interconnects. The first memory cell includes a first multilayer structure and a first variable resistance layer, the first multilayer structure including a first electrode, a first selector, and a first insulator which are stacked. The first selector and the first variable resistance layer are electrically connected in series between the one of the first interconnect and the one of the second interconnect. The first variable resistance layer is formed on a portion of a side surface of the first insulator to cover the portion without covering a residual portion.
摘要翻译：根据一个实施例，存储器件包括第一互连，第二互连和第一存储单元。第一存储器单元位于第一互连中的一个和第二互连中的一个的交叉点中。第一存储单元包括第一多层结构和第一可变电阻层，第一多层结构包括堆叠的第一电极，第一选择器和第一绝缘体。第一选择器和第一可变电阻层串联地电连接在第一互连和第二互连中的一个之间。第一可变电阻层形成在第一绝缘体的侧表面的一部分上以覆盖该部分而不覆盖剩余部分。

5. 发明申请

US20110228590A1 RESISTANCE CHANGE MEMORY 有权
标题翻译：电阻变化记忆
公开(公告)号：US20110228590A1
公开(公告)日：2011-09-22
申请号：US13072029
申请日：2011-03-25
申请人： Kenichi MUROOKA
发明人： Kenichi MUROOKA
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0033 , G11C2013/0092 , G11C2213/71 , G11C2213/72
摘要： A memory includes memory cells each includes a resistance change element and a diode, and each memory cell between one of row lines and one of column lines, a first decoder which selects one of the row lines as a selected row line, a second decoder which selects one of the column lines as a selected column line, a voltage pulse generating circuit which generates a voltage pulse, a voltage pulse shaping circuit which makes a rise time and a fall time of the voltage pulse longer, and a control circuit which applies the voltage pulse outputting from the voltage pulse shaping circuit to unselected column lines except the selected column line, and which applies a fixed potential to unselected row lines except the selected row line, in a data writing to a memory cell which is provided between the selected row line and the selected column line.
摘要翻译：存储器包括各自包括电阻变化元件和二极管的存储单元，以及行线和列线之一之间的每个存储单元，选择行行之一作为所选行行的第一解码器，第二解码器，选择列线之一作为选择的列线，产生电压脉冲的电压脉冲发生电路，使电压脉冲的上升时间和下降时间更长的电压脉冲整形电路，以及施加电压脉冲的控制电路电压脉冲从电压脉冲整形电路输出到除了所选列线之外的未选择的列线，并且在设置在所选择的行之间的存储单元的数据写入中将固定电位施加到除所选行行之外的未选行行行和所选列行。

6. 发明申请

US20110002156A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110002156A1
公开(公告)日：2011-01-06
申请号：US12695512
申请日：2010-01-28
申请人： Kenichi MUROOKA
发明人： Kenichi MUROOKA
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C13/0007 , G11C8/08 , G11C8/12 , G11C13/0004 , G11C13/0023 , G11C2213/71
摘要： A semiconductor memory device includes a plurality of first wirings; a plurality of second wirings; a plurality of memory cells positioned at respective intersections of the first wirings and the second wirings, each of the memory cells having a variable resistance element and a selective element connected to the variable resistance element in series; a first selection portion selecting the first wiring; a second selection portion selecting the second wiring; and a power source portion applying predetermined selected-wiring-voltages to a selected first wiring being selected by the first selection portion and a selected second wiring being selected by the second selection portion, respectively, and applying predetermined unselected-wiring-voltages to unselected first wirings other than the selected first wiring and unselected second wirings other than the selected second wiring, respectively. A resistance element having a predetermined resistance value is provided between the power source portion and the unselected first and second wirings.
摘要翻译：半导体存储器件包括多个第一配线; 多个第二布线; 多个存储单元，位于第一布线和第二布线的相应交点处，每个存储单元具有可变电阻元件和与可变电阻元件串联连接的选择元件; 选择第一布线的第一选择部分; 选择第二布线的第二选择部分; 以及电源部，分别对由所述第一选择部选择的所选择的第一布线和由所述第二选择部选择的所选择的第二布线分别施加预定的选择布线电压，并将预定的未选择布线电压施加到未选择的第一布线电压除了所选择的第一布线以外的布线和除所选择的第二布线以外的未选择的第二布线。在电源部分和未选择的第一和第二布线之间设置具有预定电阻值的电阻元件。

7. 发明申请

US20130148400A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20130148400A1
公开(公告)日：2013-06-13
申请号：US13313186
申请日：2011-12-07
申请人： Kenichi MUROOKA
发明人： Kenichi MUROOKA
IPC分类号： G11C5/06
CPC分类号： H01L27/2481 , G11C5/02 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2213/31 , G11C2213/32 , G11C2213/35 , G11C2213/71 , G11C2213/78 , H01L21/768 , H01L27/2454 , H01L29/66666 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1608
摘要： According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.
摘要翻译：根据一个实施例，存储器件包括第一至第三互连，存储器单元和选择器。第一至第三互连分别沿着第一至第三方向设置。存储单元包括形成在第三互连件的第一方向上彼此面对的两个侧表面上的可变电阻层。选择器将第三互连与第一互连耦合。其中一个选择器包括一个半导体层，该半导体层设置在相互连接的第三互连中的一个和第一互连中的相关一个之间，以及形成在半导体层的在第一方向上彼此相对的两个侧表面上的栅极之间的栅极绝缘膜。

8. 发明申请

US20110122676A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110122676A1
公开(公告)日：2011-05-26
申请号：US12887043
申请日：2010-09-21
申请人： Kenichi MUROOKA , Hirofumi Inoue
发明人： Kenichi MUROOKA , Hirofumi Inoue
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C2213/35 , G11C2213/71 , G11C2213/75 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/149
摘要： According to one embodiment, a semiconductor memory device includes: word lines; bit lines; an insulating film; an interlayer insulating film; and a resistance varying material. The word lines, the bit lines and the insulating film configure a field-effect transistor at each of the intersections of the word lines and the bit lines. The field-effect transistor has one of the word lines as a control electrode and one of the bit lines as a channel region. The field-effect transistor and the resistance varying material configure a memory cell having the field-effect transistor and the resistance varying material connected in parallel. Each of the bit lines includes a first surface opposing the word lines, and a second surface on an opposite side to the first surface. The resistance varying material is disposed in contact with the second surface and has a portion thereof in contact with the interlayer insulating film.
摘要翻译：根据一个实施例，半导体存储器件包括：字线; 位线绝缘膜; 层间绝缘膜; 和电阻变化材料。字线，位线和绝缘膜在字线和位线的每个交点处构成场效应晶体管。场效应晶体管具有作为控制电极的字线之一和位线之一作为沟道区。场效应晶体管和电阻变化材料配置具有并联连接的场效应晶体管和电阻变化材料的存储单元。每个位线包括与字线相对的第一表面和与第一表面相反的一侧上的第二表面。电阻变化材料设置成与第二表面接触并且其一部分与层间绝缘膜接触。

9. 发明申请

US20110299321A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110299321A1
公开(公告)日：2011-12-08
申请号：US13051574
申请日：2011-03-18
申请人： Kenichi MUROOKA
发明人： Kenichi MUROOKA
IPC分类号： G11C11/00
CPC分类号： G11C5/025 , G11C5/063 , G11C8/14 , G11C11/412 , G11C13/0007 , G11C13/0021 , G11C13/004 , G11C2013/005 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/10 , H01L45/146 , H01L45/147
摘要： A semiconductor memory device in accordance with an embodiment includes a plurality of first word lines, a plurality of bit lines, a resistance varying material, a plurality of second word lines and an insulating film. The bit lines intersect the first word lines. The resistance varying material is disposed at respective intersections of the first word lines and the bit lines. The second word lines intersect the bit lines. The insulating film is disposed at respective intersections of the second word lines and the bit lines. One of the first word lines and one of the second word lines are disposed so as to sandwich the bit lines. The second word lines, the bit lines, and the insulating film configure a field-effect transistor at respective intersections of the second word lines and the bit lines. The field-effect transistor and the resistance varying material configure one memory cell.
摘要翻译：根据实施例的半导体存储器件包括多个第一字线，多个位线，电阻变化材料，多个第二字线和绝缘膜。位线与第一个字线相交。电阻变化材料设置在第一字线和位线的相应交点处。第二个字线与位线相交。绝缘膜设置在第二字线和位线的各个交叉处。第一字线和第二字线之一之一被布置成夹住位线。第二字线，位线和绝缘膜在第二字线和位线的各个交点配置场效应晶体管。场效应晶体管和电阻变化材料配置一个存储单元。

10. 发明申请

US20110228589A1 RESISTANCE CHANGE MEMORY 有权
标题翻译：电阻变化记忆
公开(公告)号：US20110228589A1
公开(公告)日：2011-09-22
申请号：US13071943
申请日：2011-03-25
申请人： Kenichi MUROOKA
发明人： Kenichi MUROOKA
IPC分类号： G11C11/36
CPC分类号： H01L27/101 , H01L27/1021
摘要： A memory includes memory cells each includes a resistance change element and a diode. The diode comprises areas which is provided in order of a first semiconductor area with a first conductivity type, a second semiconductor area with the first conductivity type, and a third semiconductor area with a second conductivity type, from the column lines to the row lines. An atom density of impurities with the first conductivity type in the second semiconductor area is lower than that in the first semiconductor area. The diode comprises a fourth semiconductor area with the first conductivity type at an end portion in a third direction of the second semiconductor area, the third direction is perpendicular to a direction from the column lines to the row lines, and an atom density of impurities with the first conductivity type in the fourth semiconductor area is higher than that in the second semiconductor area.
摘要翻译：存储器包括各自包括电阻变化元件和二极管的存储单元。二极管包括从第一导电类型的第一半导体区域，具有第一导电类型的第二半导体区域和具有第二导电类型的第三半导体区域，从列线到行线的顺序提供的区域。在第二半导体区域中具有第一导电类型的杂质的原子密度低于第一半导体区域中的原子密度。二极管包括在第二半导体区域的第三方向上的端部处具有第一导电类型的第四半导体区域，第三方向垂直于从列线到行线的方向，并且具有第四半导体区域中的第一导电类型高于第二半导体区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式