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1. 发明申请

US20080165521A1 THREE-DIMENSIONAL ARCHITECTURE FOR SELF-CHECKING AND SELF-REPAIRING INTEGRATED CIRCUITS 审中-公开
标题翻译：用于自检和自修复集成电路的三维架构
公开(公告)号：US20080165521A1
公开(公告)日：2008-07-10
申请号：US11621188
申请日：2007-01-09
申请人： KERRY BERNSTEIN , Paul William Coteus , Ibrahim (Abe) M. Elfadel , Philip George Emma , Kathryn W. Guarini , Thomas Fleischman , Allan Mark Hartstein , Ruchir Puri , Mark B. Ritter , Jeannine Madelyn Trewhella , Albert M. Young
发明人： KERRY BERNSTEIN , Paul William Coteus , Ibrahim (Abe) M. Elfadel , Philip George Emma , Kathryn W. Guarini , Thomas Fleischman , Allan Mark Hartstein , Ruchir Puri , Mark B. Ritter , Jeannine Madelyn Trewhella , Albert M. Young
IPC分类号： H05K7/00 , H01L21/50
CPC分类号： H01L24/83 , H01L21/6835 , H01L21/8221 , H01L24/26 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L27/0688 , H01L2221/68354 , H01L2224/8385 , H01L2225/06524 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/07802 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043
摘要： A three-dimensional architecture chip includes a base chip including a unit integrated thereon and configured to perform electrical signal operations. An active layer is separately fabricated from the base layer. The active layer includes a component to service the unit of the base chip. The active layer is bonded to the base chip such that the component is aligned in vertical proximity of the unit. An electrical connection connects the unit to the component through vertical layers of at least one of the base chip and the active layer.
摘要翻译：三维结构芯片包括基本芯片，其包括集成在其上并被配置为执行电信号操作的单元。从基层分开制造有源层。有源层包括用于服务于基片的单元的部件。有源层被结合到基片，使得该元件在该单元的垂直方向上对准。电连接通过基底芯片和有源层中的至少一个的垂直层将单元连接到部件。

2. 发明授权

US07684224B2 Structure comprising 3-dimensional integrated circuit architecture, circuit structure, and instructions for fabrication thereof 有权
标题翻译：包括三维集成电路架构，电路结构及其制造说明的结构
公开(公告)号：US07684224B2
公开(公告)日：2010-03-23
申请号：US11768210
申请日：2007-06-26
申请人： Kerry Bernstein , Paul William Coteus , Philip George Emma
发明人： Kerry Bernstein , Paul William Coteus , Philip George Emma
IPC分类号： G11C5/02
CPC分类号： H01L21/6835 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/1052 , H01L2221/68359 , H01L2225/06541 , H01L2924/14 , H01L2924/1433 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105
摘要： An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.
摘要翻译：其制造的集成电路设计，结构和方法包括至少一个逻辑器件层和至少两个额外的分开的存储器阵列层。对于设置在其中的特定类型的逻辑设备或存储器件，逻辑器件层和至少两个存储器阵列层中的每一个被独立地优化。优选地还设置在逻辑器件层内的是阵列读出放大器，存储器阵列输出驱动器和类似的高性能电路，否则通常设置在存储器阵列层衬底内。所有层可以独立供电以提供额外的性能增强。

3. 发明授权

US06292903B1 Smart memory interface 失效
标题翻译：智能内存界面
公开(公告)号：US06292903B1
公开(公告)日：2001-09-18
申请号：US09106639
申请日：1998-06-29
申请人： Paul William Coteus , Daniel Mark Dreps , Frank Ferraiolo
发明人： Paul William Coteus , Daniel Mark Dreps , Frank Ferraiolo
IPC分类号： G06F104
CPC分类号： G06F13/1689
摘要： A method and apparatus are disclosed for initiating a start-up operation of a system (1′) having a master device (1) and a slave device (14a-14n). The method comprises steps of: A) exercising the slave device (14a-14n) using the master device (1) to determine a temporal range within which temporal relationships of electrical signals need to be set in order to operate the system (1′) without error; B) setting the temporal relationships of the electrical signals so as to be within the determined temporal range; and C) storing a record of the determined temporal range, for subsequent use in operating the system (1′). In one embodiment of the invention, the system (1′) includes a memory control system of a computer system (1″), and the slave device (14a-14n) includes memory devices of the computer system (1″). The method of the invention substantially compensates for any differences in times of arrival for data being transferred from the master device (1) to the slave device (14a-14n), and vice versa, and thus minimizes the possibility of read/write errors being encountered, while increasing the overall processing speed and efficiency of the system (1′).
摘要翻译：公开了一种用于启动具有主设备（1）和从设备（14a-14n）的系统（1'）的启动操作的方法和装置。该方法包括以下步骤：A）使用主设备（1）来执行从设备（14a-14n）以确定需要设置电信号的时间关系以便操作系统（1'）的时间范围，没有错误; B）将电信号的时间关系设置在所确定的时间范围内; 和C）存储所确定的时间范围的记录，以供随后在操作系统（1'）中使用。在本发明的一个实施例中，系统（1'）包括计算机系统（1“）的存储器控制系统，并且从设备（14a-14n）包括计算机系统（1”）的存储设备。本发明的方法基本上补偿从主设备（1）传送到从设备（14a-14n）的数据的到达时间的任何差异，反之亦然，从而使读/写错误的可能性最小化同时提高系统的整体处理速度和效率（1'）。

4. 发明授权

US6127840A Dynamic line termination clamping circuit 失效
标题翻译：动态线路终端钳位电路
公开(公告)号：US6127840A
公开(公告)日：2000-10-03
申请号：US42912
申请日：1998-03-17
申请人： Paul William Coteus , Daniel Mark Dreps , Frank David Ferraiolo
发明人： Paul William Coteus , Daniel Mark Dreps , Frank David Ferraiolo
IPC分类号： H03K5/007 , H03K19/0175 , H04L25/02 , H03K17/16 , H03K19/003
CPC分类号： H04L25/0278 , H04L25/028 , H04L25/0292
摘要： A first circuit and a second circuit are connected by a pumped signal line that conducts a signal having a plurality of states. A dynamic termination circuit is connected to the pumped signal line. The dynamic termination circuit includes a switch responsive to the signal conducted by the pumped signal line such that the dynamic termination circuit is enabled only in response to certain of the plurality of states of the signal. In one embodiment, the switch is a first transistor that is coupled in series with a first impedance between a first reference voltage and an intermediate node. In this embodiment, the dynamic termination circuit further includes a second transistor coupled in series with a second impedance between a second reference voltage and the intermediate node and only first and second inverters that are each coupled between the intermediate node and the control input of a respective one of the first transistor and the second transistor.
摘要翻译：第一电路和第二电路通过导通具有多个状态的信号的泵浦信号线连接。动态终端电路连接到泵浦信号线。动态终端电路包括响应于由泵浦信号线传导的信号的开关，使得动态终端电路仅在响应于信号的多个状态中的某些状态时被使能。在一个实施例中，开关是与第一参考电压和中间节点之间的第一阻抗串联耦合的第一晶体管。在该实施例中，动态终端电路还包括与第二参考电压和中间节点之间的第二阻抗串联耦合的第二晶体管，并且仅包括第一和第二反相器，每个反相器耦合在相应的中间节点和控制输入端第一晶体管和第二晶体管之一。

5. 发明授权

US5780925A Lead frame package for electronic devices 失效
标题翻译：电子设备引线框架封装
公开(公告)号：US5780925A
公开(公告)日：1998-07-14
申请号：US569561
申请日：1995-12-08
申请人： Thomas Mario Cipolla , Paul William Coteus
发明人： Thomas Mario Cipolla , Paul William Coteus
IPC分类号： H01L21/60 , H01L23/495 , H01L23/50 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/06 , H01L23/49503 , H01L23/4951 , H01L23/49541 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/49171 , H01L2224/49431 , H01L2224/49433 , H01L2225/06562 , H01L2924/00014 , H01L2924/01014 , H01L2924/01031 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15183 , H01L2924/15787 , H01L2924/181 , H01L2924/30107
摘要： An electronic device packaging structure is described which contains a lead frame on which the electronic device is disposed. The electronic device has contact locations at one edge thereof. The lead frame has leads which extend under the electronic device and inwardly from the opposite direction. Wires are wire bonded between electronic device contact locations and the beam leads which extend under the electronic device and the ends of the leads which extend inwardly from the opposite direction. Two electronic devices are stacked in at an offset with respect to each to expose contact locations on the surface of each electronic device at an edge of each electronic device to form a stepped surface exposing a plurality of electronic device contact locations. Preferably, the chips are identical and rotated 180.degree. with respect to each other. Some of the leads of the lead frame for the double dense memory extend continuously under the stack to provide signal inputs through bit, address, control, power and ground inputs to the electronic devices. These inputs are common between the adjacent chips. Wires are bonded from contact locations on each chip to common leads. If a lead is common and cannot be mixed with another common lead, for example, a control line, it is located at the center of the lead frame. Other leads are provided which are not common between the two chips, for example chip select lines. Wires are bonded between the contact locations on each chip and at least one of the common leads of the lead frame.
摘要翻译：描述了一种电子设备包装结构，其包含设置电子设备的引线框架。电子设备在其一个边缘处具有接触位置。引线框架具有在电子设备下方延伸并且从相反方向向内延伸的引线。导线在电子器件接触位置之间被引线接合，并且在电子器件下面延伸的光束引线和从相反方向向内延伸的引线的端部。两个电子器件相对于每个电子器件以偏移方式堆叠以暴露每个电子器件的边缘处的每个电子器件的表面上的接触位置，以形成露出多个电子器件接触位置的台阶表面。优选地，芯片相同并相对于彼此旋转180度。双密度存储器的引线框架的一些引线在堆叠下连续延伸，以通过位，地址，控制，电源和接地输入向电子设备提供信号输入。这些输入在相邻芯片之间是共同的。电线从每个芯片上的接触位置连接到公共导线。如果引线是常见的，并且不能与另一个公共引线（例如，控制线）混合，则它位于引线框架的中心。提供了在两个芯片之间不常见的其它引线，例如芯片选择线。电线结合在每个芯片上的接触位置和引线框架的至少一个公共引线之间。

6. 发明申请

US20080026628A1 Pin Grid Array Zero Insertion Force Connectors Configurable for Supporting Large Pin Counts 有权
标题翻译：针脚阵列零插入力连接器可配置为支持大引脚数
公开(公告)号：US20080026628A1
公开(公告)日：2008-01-31
申请号：US11763499
申请日：2007-06-15
申请人： Gareth Geoffrey Hougham , William Louis Brodsky , Thomas M. Cipolla , Paul William Coteus , Ronald Malfatt
发明人： Gareth Geoffrey Hougham , William Louis Brodsky , Thomas M. Cipolla , Paul William Coteus , Ronald Malfatt
IPC分类号： H01R13/625
CPC分类号： H01R13/193 , H05K7/1007
摘要： A PGA socket including a plurality of sub-socket components, which when used in combination forms a larger effective socket, includes multiple apertures configured to receive corresponding pins of an IC. The PGA socket further includes multiple contact members, each of the contact members corresponding to a respective one of the apertures. The contact members are configured to movably engage corresponding pins of the IC upon respective movement of the apertures so as to provide electrical and mechanical contact thereto. Each of the sub-socket components is configured to mechanically engage at least one of the other sub-socket components such that the contact members in each of the sub-socket components are capable of electrically connecting to corresponding pins of the IC substantially simultaneously.
摘要翻译：包括多个子插座部件的PGA插座，当组合使用时形成较大的有效插座，包括配置成接收IC的相应引脚的多个孔。 PGA插座还包括多个接触构件，每个接触构件对应于相应的一个孔。接触构件被构造成在孔的相应移动时可移动地接合IC的相应销，以便提供与其的电和机械接触。每个子插座部件被构造成机械地接合其他子插座部件中的至少一个，使得每个子插座部件中的接触部件能够基本上同时电连接到IC的相应引脚。

7. 发明授权

US06919515B2 Stress accommodation in electronic device interconnect technology for millimeter contact locations 有权
标题翻译：用于毫米接触位置的电子设备互连技术中的应力调节
公开(公告)号：US06919515B2
公开(公告)日：2005-07-19
申请号：US09768372
申请日：2001-01-23
申请人： Edmund David Blackshear , Thomas Mario Cipolla , Paul William Coteus
发明人： Edmund David Blackshear , Thomas Mario Cipolla , Paul William Coteus
IPC分类号： H05K3/12 , H05K3/34 , H05K1/16
CPC分类号： H05K3/3436 , H01L2224/0401 , H01L2224/05555 , H01L2224/13014 , H05K3/1216 , H05K3/3484 , H05K2201/09381 , Y02P70/613 , H01L2924/00012 , H01L2924/00014
摘要： The providing of an array interface of conductive joint members for use in forming interconnections between mating surfaces such as a pad on a surface mount electronic device and contacts on a circuit card where one portion of the conductive joint members are of a relatively elongated or oval outline and are oriented with the longer dimension in one direction to accommodate wiring spacing and another portion oriented in a different direction for accommodating expansion stress. In manufacturing when the relatively elongated shape is oriented with the longer dimension along the wiping motion direction in a screen type forming of the conductive joint members the slurry of material that is to be the conductive joint members fills the openings in the screen more reliably and the areas of the conductive members are more uniform. The invention provides the advantages of an increase in the number of wiring lines, an increase in uniformity of wiped screen deposition conductive joint member formation, ability to employ more than one out of chip and wiring levels in expansion mismatch stress relief, and ability by conductive joint member dimensional alignment to improve reliability and flexibility.
摘要翻译：提供用于在配合表面之间形成互连的导电接头构件的阵列接口，例如表面安装电子设备上的焊盘和电路卡上的触点，其中导电接头构件的一部分具有相对细长或椭圆形的轮廓并且在一个方向上具有更长的尺寸以适应布线间距，并且另一部分沿不同的方向定向以适应膨胀应力。在制造中，当形成导电接头部件的筛网形式中相对细长的形状沿着擦拭运动方向具有更长的尺寸时，作为导电接头部件的材料的浆料更可靠地填充筛网中的开口，并且导电构件的区域更均匀。本发明提供了布线数量增加，擦拭屏幕沉积导电接头构件形成的均匀性增加的优点，在扩展失配应力消除中使用多于一个芯片和布线水平的能力以及导电性能联合构件尺寸对齐以提高可靠性和灵活性。

8. 发明授权

US06276844B1 Clustered, buffered simms and assemblies thereof 失效
标题翻译：聚集的，缓冲的simms及其组件
公开(公告)号：US06276844B1
公开(公告)日：2001-08-21
申请号：US08744006
申请日：1996-10-30
申请人： Paul William Coteus , Ralph Herman Genz , Alphonso P. Lanzetta , Warren Edward Maule , Daniel Julius Phipps , James K. Tam , James Donald Wagoner
发明人： Paul William Coteus , Ralph Herman Genz , Alphonso P. Lanzetta , Warren Edward Maule , Daniel Julius Phipps , James K. Tam , James Donald Wagoner
IPC分类号： G06F1200
CPC分类号： G11C5/06 , G06F1/183 , G11C5/04
摘要： A data processing system including an improved method and apparatus for the arrangement and interconnection between electronic devices to improve system cycle time. The apparatus possesses a) a plurality of: memory SIMMs, memory devices on the noted memory SIMMs and registers; b) a clock; c) means for connecting signals between the memory devices on the memory SIMMs and the registers; and d) means for connecting signals between the memory devices on the memory SIMMs and the clocks.
摘要翻译：一种数据处理系统，包括用于在电子设备之间布置和互连的改进的方法和装置，以改善系统周期时间。该装置具有a）多个存储器SIMM，所述存储器SIMM和寄存器中的存储器件; b）时钟 c）用于连接存储器SIMM和寄存器上的存储器件之间的信号的装置; 以及d）用于连接存储器SIMM和时钟之间的存储器件之间的信号的装置。

9. 发明授权

US07418068B2 Data capture technique for high speed signaling 失效
标题翻译：高速信号数据采集技术
公开(公告)号：US07418068B2
公开(公告)日：2008-08-26
申请号：US10468992
申请日：2002-02-25
申请人： Wayne Melvin Barrett , Dong Chen , Paul William Coteus , Alan Gene Gara , Rory Jackson , Gerard Vincent Kopcsay , Ben Jesse Nathanson , Paylos Michael Vranas , Todd E. Takken
发明人： Wayne Melvin Barrett , Dong Chen , Paul William Coteus , Alan Gene Gara , Rory Jackson , Gerard Vincent Kopcsay , Ben Jesse Nathanson , Paylos Michael Vranas , Todd E. Takken
IPC分类号： H04L7/00
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.
摘要翻译：用于高速信令的数据捕获技术，以允许异步数据流的最佳采样。这种技术允许极高的数据速率，并且不要求在源同步系统中进行数据发送时钟。本发明还提供了用于自动调整用于最佳两比特双向（SiBiDi）信令的传输延迟的硬件机制。

10. 发明申请

US20080026627A1 PIN GRID ARRAY ZERO INSERTION FORCE CONNECTORS CONFIGURABLE FOR SUPPORTING LARGE PIN COUNTS 有权
标题翻译： PIN网格阵列插入力连接器可配置为支持大量PIN码
公开(公告)号：US20080026627A1
公开(公告)日：2008-01-31
申请号：US11496153
申请日：2006-07-31
申请人： Gareth Geoffrey Hougham , William Louis Brodsky , Thomas M. Cipolla , Paul William Coteus , Ronald Malfatt
发明人： Gareth Geoffrey Hougham , William Louis Brodsky , Thomas M. Cipolla , Paul William Coteus , Ronald Malfatt
IPC分类号： H01R4/50
CPC分类号： H01R13/193 , H05K7/1007
摘要： A PGA socket including a plurality of sub-socket components, which when used in combination forms a larger effective socket, includes multiple apertures configured to receive corresponding pins of an IC. The PGA socket further includes multiple contact members, each of the contact members corresponding to a respective one of the apertures. The contact members are configured to movably engage corresponding pins of the IC upon respective movement of the apertures so as to provide electrical and mechanical contact thereto. Each of the sub-socket components is configured to mechanically engage at least one of the other sub-socket components such that the contact members in each of the sub-socket components are capable of electrically connecting to corresponding pins of the IC substantially simultaneously.
摘要翻译：包括多个子插座部件的PGA插座，当组合使用时形成较大的有效插座，包括配置成接收IC的相应引脚的多个孔。 PGA插座还包括多个接触构件，每个接触构件对应于相应的一个孔。接触构件被构造成在孔的相应移动时可移动地接合IC的相应销，以便提供与其的电和机械接触。每个子插座部件被构造成机械地接合其他子插座部件中的至少一个，使得每个子插座部件中的接触部件能够基本上同时电连接到IC的相应引脚。

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