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1. 发明授权

US08984322B2 Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed 有权
标题翻译：配置为以不同时钟速度运行的多个链路的时钟速度切换的设备和切换时钟速度的方法
公开(公告)号：US08984322B2
公开(公告)日：2015-03-17
申请号：US13461041
申请日：2012-05-01
申请人： Kevin D. Senohrabek , Natale Barbiero , Gordon F. Caruk
发明人： Kevin D. Senohrabek , Natale Barbiero , Gordon F. Caruk
IPC分类号： G06F1/08 , G06F13/40 , G06F1/06 , G06F1/10 , G06F1/12
CPC分类号： G06F13/4022 , G06F1/06 , G06F1/10 , G06F1/12 , G06F2213/0026
摘要： A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.
摘要翻译：公开了一种被配置为切换以不同时钟速度运行的多个链路的时钟速度的装置和用于切换时钟信号的方法。分频器从与源时钟信号不同的频率导出多个时钟信号。时钟切换控制器选择由多个链路端口请求的数据速率之中的最大数据速率，并将所选择的最大数据速率的发送时钟信号与每个端口的时钟使能信号一起输出到端口。每个时钟使能信号选择性地使能发送时钟信号以匹配每个端口请求的数据速率。时钟速度可以按照端口在已知时间段内无毛刺的要求进行选择和更新，而不会中断任何其他端口上的数据传输。

2. 发明申请

US20120221883A1 DEVICE CONFIGURED TO SWITCH A CLOCK SPEED FOR MULTIPLE LINKS RUNNING AT DIFFERENT CLOCK SPEEDS AND METHOD FOR SWITCHING THE CLOCK SPEED 审中-公开
标题翻译：配置为在不同时钟速度下运行多个链接的时钟速度切换的设备和用于切换时钟速度的方法
公开(公告)号：US20120221883A1
公开(公告)日：2012-08-30
申请号：US13461041
申请日：2012-05-01
申请人： Kevin D. Senohrabek , Natale Barbiero , Gordon F. Caruk
发明人： Kevin D. Senohrabek , Natale Barbiero , Gordon F. Caruk
IPC分类号： G06F1/08
CPC分类号： G06F13/4022 , G06F1/06 , G06F1/10 , G06F1/12 , G06F2213/0026
摘要： A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.
摘要翻译：公开了一种被配置为切换以不同时钟速度运行的多个链路的时钟速度的装置和用于切换时钟信号的方法。分频器从与源时钟信号不同的频率导出多个时钟信号。时钟切换控制器选择由多个链路端口请求的数据速率之中的最大数据速率，并将所选择的最大数据速率的发送时钟信号与每个端口的时钟使能信号一起输出到端口。每个时钟使能信号选择性地使能发送时钟信号以匹配每个端口请求的数据速率。时钟速度可以按照端口在已知时间段内无毛刺的要求进行选择和更新，而不会中断任何其他端口上的数据传输。

3. 发明授权

US08190944B2 Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed 有权
标题翻译：配置为以不同时钟速度运行的多个链路的时钟速度切换的设备和切换时钟速度的方法
公开(公告)号：US08190944B2
公开(公告)日：2012-05-29
申请号：US12635942
申请日：2009-12-11
申请人： Kevin D. Senohrabek , Natale Barbiero , Gordon F. Caruk
发明人： Kevin D. Senohrabek , Natale Barbiero , Gordon F. Caruk
IPC分类号： G06F12/06 , H04B10/24
CPC分类号： G06F13/4022 , G06F1/06 , G06F1/10 , G06F1/12 , G06F2213/0026
摘要： A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.
摘要翻译：公开了一种被配置为切换以不同时钟速度运行的多个链路的时钟速度的装置和用于切换时钟信号的方法。分频器从与源时钟信号不同的频率导出多个时钟信号。时钟切换控制器选择由多个链路端口请求的数据速率之中的最大数据速率，并将所选择的最大数据速率的发送时钟信号与每个端口的时钟使能信号一起输出到端口。每个时钟使能信号选择性地使能发送时钟信号以匹配每个端口请求的数据速率。时钟速度可以按照端口在已知时间段内无毛刺的要求进行选择和更新，而不会中断任何其他端口上的数据传输。

4. 发明申请

US20110145622A1 DEVICE CONFIGURED TO SWITCH A CLOCK SPEED FOR MULTIPLE LINKS RUNNING AT DIFFERENT CLOCK SPEEDS AND METHOD FOR SWITCHING THE CLOCK SPEED 有权
标题翻译：配置为在不同时钟速度下运行多个链接的时钟速度切换的设备和用于切换时钟速度的方法
公开(公告)号：US20110145622A1
公开(公告)日：2011-06-16
申请号：US12635942
申请日：2009-12-11
申请人： Kevin D. Senohrabek , Natale Barbiero , Gordon F. Caruk
发明人： Kevin D. Senohrabek , Natale Barbiero , Gordon F. Caruk
IPC分类号： G06F1/12
CPC分类号： G06F13/4022 , G06F1/06 , G06F1/10 , G06F1/12 , G06F2213/0026
摘要： A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.
摘要翻译：公开了一种被配置为切换以不同时钟速度运行的多个链路的时钟速度的装置和用于切换时钟信号的方法。分频器从与源时钟信号不同的频率导出多个时钟信号。时钟切换控制器选择由多个链路端口请求的数据速率之中的最大数据速率，并将所选择的最大数据速率的发送时钟信号与每个端口的时钟使能信号一起输出到端口。每个时钟使能信号选择性地使能发送时钟信号以匹配每个端口请求的数据速率。时钟速度可以按照端口在已知时间段内无毛刺的要求进行选择和更新，而不会中断任何其他端口上的数据传输。

5. 发明申请

US20110161547A1 METHOD AND DEVICE FOR DISABLING A HIGHER VERSION OF A COMPUTER BUS AND INTERCONNECTION PROTOCOL FOR INTEROPERABILITY WITH A DEVICE COMPLIANT TO A LOWER VERSION OF THE COMPUTER BUS AND INTERCONNECTION PROTOCOL 有权
标题翻译：用于禁用计算机总线和互连协议的较高版本的方法和设备，用于与符合计算机总线和互连协议的较低版本的设备的互操作性
公开(公告)号：US20110161547A1
公开(公告)日：2011-06-30
申请号：US12647047
申请日：2009-12-24
申请人： Natale Barbiero , Gordon F. Caruk
发明人： Natale Barbiero , Gordon F. Caruk
IPC分类号： G06F13/00
CPC分类号： G06F13/00 , G06F13/385
摘要： A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol.
摘要翻译：公开了一种用于禁用较低版本的计算机总线和互连协议（例如，外围组件互连Express（PCIe）2.0或更高版本）的方法和设备，用于与符合较低版本协议的接收机的互操作性。设备检测到接收机的存在，并开始链路训练。在链接训练期间，计算链接训练失败的次数或经过的时间。只要链路训练失败的次数或者经过的时间低于预定的阈值，该设备就会发送训练序列，该训练序列包括根据设备在每个通道上支持的更高版本的协议来设置接收机的训练序列。如果链路训练失败的次数或经过的时间达到预定的阈值，则设备发送训练序列，其包括根据协议的较低版本设置的符号。

6. 发明授权

US08301813B2 Method and device for disabling a higher version of a computer bus and interconnection protocol for interoperability with a device compliant to a lower version of the computer bus and interconnection protocol 有权
标题翻译：用于禁用更高版本的计算机总线和互连协议的方法和设备，用于与符合计算机总线和互连协议的较低版本的设备的互操作性
公开(公告)号：US08301813B2
公开(公告)日：2012-10-30
申请号：US12647047
申请日：2009-12-24
申请人： Natale Barbiero , Gordon F. Caruk
发明人： Natale Barbiero , Gordon F. Caruk
IPC分类号： G06F13/00
CPC分类号： G06F13/00 , G06F13/385
摘要： A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol.
摘要翻译：公开了一种用于禁用较低版本的计算机总线和互连协议（例如，外围组件互连Express（PCIe）2.0或更高版本）的方法和设备，用于与符合较低版本协议的接收机的互操作性。设备检测到接收机的存在，并开始链路训练。在链接训练期间，计算链接训练失败的次数或经过的时间。只要链路训练失败的次数或者经过的时间低于预定的阈值，该设备就会发送训练序列，该训练序列包括根据设备在每个通道上支持的更高版本的协议来设置接收机的训练序列。如果链路训练失败的次数或经过的时间达到预定的阈值，则设备发送训练序列，其包括根据协议的较低版本设置的符号。

7. 发明授权

US08933947B2 Reading a local memory of a processing unit 有权
标题翻译：读取处理单元的本地存储器
公开(公告)号：US08933947B2
公开(公告)日：2015-01-13
申请号：US12719628
申请日：2010-03-08
申请人： David I. J. Glen , Philip J. Rogers , Gordon F. Caruk , Gongxian Jeffrey Cheng , Mark Hummel , Stephen Patrick Thompson , Anthony Asaro
发明人： David I. J. Glen , Philip J. Rogers , Gordon F. Caruk , Gongxian Jeffrey Cheng , Mark Hummel , Stephen Patrick Thompson , Anthony Asaro
IPC分类号： G06T15/00 , G06F12/02 , G06F12/08 , G06F13/00 , G06F3/14 , G09G5/00 , G09G5/36 , G09G5/393
CPC分类号： G06F3/14 , G09G5/001 , G09G5/363 , G09G5/393 , G09G2350/00 , G09G2360/121
摘要： Disclosed herein are systems, apparatuses, and methods for enabling efficient reads to a local memory of a processing unit. In an embodiment, a processing unit includes an interface and a buffer. The interface is configured to (i) send a request for a portion of data in a region of a local memory of an other processing unit and (ii) receive, responsive to the request, all the data from the region. The buffer is configured to store the data from the region of the local memory of the other processing unit.
摘要翻译：这里公开了用于实现对处理单元的本地存储器的高效读取的系统，装置和方法。在一个实施例中，处理单元包括接口和缓冲器。该接口被配置为（i）向另一个处理单元的本地存储器的区域中的一部分数据发送请求，以及（ii）响应该请求从该区域接收所有数据。缓冲器被配置为存储来自另一处理单元的本地存储器的区域的数据。

8. 发明申请

US20120017026A1 System and Method for Increased Efficiency PCI Express Transaction 有权
标题翻译：提高PCI Express事务的系统和方法
公开(公告)号：US20120017026A1
公开(公告)日：2012-01-19
申请号：US12837636
申请日：2010-07-16
申请人： Betty Luk , Gordon F. Caruk
发明人： Betty Luk , Gordon F. Caruk
IPC分类号： G06F13/36
CPC分类号： G06F13/4282 , G06F2213/0026
摘要： A system and method using new PCI Express transaction layer packet headers so that unchanged header information within a burst of transactions does not need to be re-transmitted. After the first full packet header of a burst is sent, subsequent packet headers in the burst are smaller. Thus, more reduced headers can be transmitted over time with a resulting increased efficiency. Both sides of the PCI Express transaction must support this system and method for this approach to be enabled. Once enabled, both the PCI Express transmitter and receiver can use the regular full header PCI Express packets as well as the reduced header packets.
摘要翻译：一种使用新的PCI Express事务层分组报头的系统和方法，使得不需要重新发送事务突发内的未改变的报头信息。在发送突发的第一个完整分组报头之后，突发中的后续分组报头较小。因此，可以随着时间推移更多的减少的报头，从而提高效率。 PCI Express事务的双方必须支持该系统和方法来启用此方法。一旦启用，PCI Express发送器和接收器都可以使用常规全标头PCI Express数据包以及减少的标头数据包。

9. 发明申请

US20110057939A1 Reading a Local Memory of a Processing Unit 有权
标题翻译：读取处理单元的本地存储器
公开(公告)号：US20110057939A1
公开(公告)日：2011-03-10
申请号：US12719628
申请日：2010-03-08
申请人： David I.J. GLEN , Philip J. Rogers , Gordon F. Caruk , Gongxian Jeffrey Cheng , Mark Hummel , Stephen Patrick Thompson , Anthony Asaro
发明人： David I.J. GLEN , Philip J. Rogers , Gordon F. Caruk , Gongxian Jeffrey Cheng , Mark Hummel , Stephen Patrick Thompson , Anthony Asaro
IPC分类号： G06T15/00 , G06F12/02 , G06F12/08 , G06F13/00
CPC分类号： G06F3/14 , G09G5/001 , G09G5/363 , G09G5/393 , G09G2350/00 , G09G2360/121
摘要： Disclosed herein are systems, apparatuses, and methods for enabling efficient reads to a local memory of a processing unit. In an embodiment, a processing unit includes an interface and a buffer. The interface is configured to (i) send a request for a portion of data in a region of a local memory of an other processing unit and (ii) receive, responsive to the request, all the data from the region. The buffer is configured to store the data from the region of the local memory of the other processing unit.
摘要翻译：这里公开了用于实现对处理单元的本地存储器的高效读取的系统，装置和方法。在实施例中，处理单元包括接口和缓冲器。该接口被配置为（i）向另一个处理单元的本地存储器的区域中的一部分数据发送请求，以及（ii）响应该请求从该区域接收所有数据。缓冲器被配置为存储来自另一处理单元的本地存储器的区域的数据。

10. 发明申请

US20130163489A1 Method and System Providing Interoperability Between Wireless Gigabit Alliance I/O PAL and A/V PAL Devices 审中-公开
标题翻译：提供无线千兆位联盟I / O PAL和A / V PAL设备之间的互操作性的方法和系统
公开(公告)号：US20130163489A1
公开(公告)日：2013-06-27
申请号：US13336455
申请日：2011-12-23
申请人： Keith Shu Key Lee , Syed Hussain , Lei Zhang , Gordon F. Caruk , David I.J. Glen
发明人： Keith Shu Key Lee , Syed Hussain , Lei Zhang , Gordon F. Caruk , David I.J. Glen
IPC分类号： H04W4/00 , H04J3/22
CPC分类号： H04W4/18
摘要： A method and system are provided for transmitting wireless signals from a source station having a WGA IO PAL device to one or more destination stations having WGA AV PAL device according to a protocol adaptation layer translation mechanism whereby received data and control packets formatted in accordance with a first protocol adaptation layer or translated into translated data and control packets formatted in accordance with a second different protocol adaptation layer prior to conveyance in accordance with the second different protocol adaptation layer.
摘要翻译：提供了一种方法和系统，用于根据协议适配层转换机制将具有WGA IO PAL设备的源站的无线信号传输到具有WGA AV PAL设备的一个或多个目的地站，从而接收到的数据和按照第一协议适配层或者根据第二不同协议适配层在传送之前根据第二不同协议适配层转换成翻译数据和控制分组格式化的分组。

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