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1. 发明授权

US08045670B2 Interpolative all-digital phase locked loop 有权
标题翻译：内插全数字锁相环
公开(公告)号：US08045670B2
公开(公告)日：2011-10-25
申请号：US12022931
申请日：2008-01-30
申请人： Khurram Waheed , Robert Bogdan Staszewski , John L. Wallberg , Sudheer K. Vemulapalli
发明人： Khurram Waheed , Robert Bogdan Staszewski , John L. Wallberg , Sudheer K. Vemulapalli
IPC分类号： H03D3/24
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. An interpolator is coupled to the phase detection circuit for performing a sample rate conversion between the reference clock and the clock derived from the RF clock signal.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。内插器耦合到相位检测电路，用于执行参考时钟和从RF时钟信号导出的时钟之间的采样率转换。

2. 发明申请

US20080317188A1 Digital Phase Locked Loop with Integer Channel Mitigation 有权
标题翻译：具有整数通道缓解的数字锁相环
公开(公告)号：US20080317188A1
公开(公告)日：2008-12-25
申请号：US12024881
申请日：2008-02-01
申请人： Robert Bogdan Staszewski , Sudheer K. Vemulapalli , John L. Wallberg , Khurram Waheed
发明人： Robert Bogdan Staszewski , Sudheer K. Vemulapalli , John L. Wallberg , Khurram Waheed
IPC分类号： H04L7/00
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal with a plurality of phases. A switch is coupled to receive the RF clock, and is operative to select one of the plurality of phases. A phase detection circuit is coupled to the switch and is operable to receive a selected phase and to provide digital phase error samples indicative of a time difference between the reference clock and the selected phase.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生具有多个相位的RF时钟信号。耦合开关以接收RF时钟，并且可操作以选择多个相位中的一个。相位检测电路耦合到开关并且可操作以接收所选择的相位并且提供指示参考时钟和所选相位之间的时间差的数字相位误差样本。

3. 发明授权

US08050375B2 Digital phase locked loop with integer channel mitigation 有权
标题翻译：数字锁相环，整数通道缓解
公开(公告)号：US08050375B2
公开(公告)日：2011-11-01
申请号：US12024881
申请日：2008-02-01
申请人： Robert Bogdan Staszewski , Sudheer K. Vemulapalli , John L. Wallberg , Khurram Waheed
发明人： Robert Bogdan Staszewski , Sudheer K. Vemulapalli , John L. Wallberg , Khurram Waheed
IPC分类号： H03D3/24
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal with a plurality of phases. A switch is coupled to receive the RF clock, and is operative to select one of the plurality of phases. A phase detection circuit is coupled to the switch and is operable to receive a selected phase and to provide digital phase error samples indicative of a time difference between the reference clock and the selected phase.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生具有多个相位的RF时钟信号。耦合开关以接收RF时钟，并且可操作以选择多个相位中的一个。相位检测电路耦合到开关并且可操作以接收所选择的相位并且提供指示参考时钟和所选相位之间的时间差的数字相位误差样本。

4. 发明申请

US20080317187A1 Interpolative All-Digital Phase Locked Loop 有权
标题翻译：插值全数字锁相环
公开(公告)号：US20080317187A1
公开(公告)日：2008-12-25
申请号：US12022931
申请日：2008-01-30
申请人： Khurram Waheed , Robert Bogdan Staszewski , John L. Wallberg , Sudheer K. Vemulapalli
发明人： Khurram Waheed , Robert Bogdan Staszewski , John L. Wallberg , Sudheer K. Vemulapalli
IPC分类号： H04L7/00
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. An interpolator is coupled to the phase detection circuit for performing a sample rate conversion between the reference clock and the clock derived from the RF clock signal.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。内插器耦合到相位检测电路，用于执行参考时钟和从RF时钟信号导出的时钟之间的采样率转换。

5. 发明授权

US08126401B2 Transmitter PLL with bandwidth on demand 有权
标题翻译：发射器PLL，带宽需求
公开(公告)号：US08126401B2
公开(公告)日：2012-02-28
申请号：US12412790
申请日：2009-03-27
申请人： Robert Bogdan Staszewski , Khurram Waheed , Sudheer K. Vemulapalli , Manouchehr Entezari , Imran Bashir
发明人： Robert Bogdan Staszewski , Khurram Waheed , Sudheer K. Vemulapalli , Manouchehr Entezari , Imran Bashir
IPC分类号： H04B1/00
CPC分类号： H03L7/085 , H03L7/093 , H03L7/0991 , H03L2207/50 , H04L27/361
摘要： An embodiment of the present invention provides transmitter having a phase locked loop that has a dynamically controllable loop bandwidth. A transmit modulator is coupled to the PLL for performing vector modulation in response to transmission symbols. Each transmission symbol comprises an amplitude signal and a phase signal. A controller is coupled to the PLL and to the transmit modulator and is operable to detect when a criteria of the transmission symbols crosses a threshold and to adjust loop bandwidth in response to crossing the threshold. The criteria of the transmission symbols may be a function of the amplitude signal or a function of the phase signal, and may be the amplitude signal, a first derivative of the amplitude signal, a second derivative of the amplitude signal, a square of the amplitude signal, a derivative of the amplitude signal squared, the phase signal, or a derivative of the phase signal.
摘要翻译：本发明的一个实施例提供具有锁相环的发射机，其具有动态可控的环路带宽。发射调制器耦合到PLL以响应于发射符号执行矢量调制。每个发送符号包括振幅信号和相位信号。控制器耦合到PLL和发射调制器，并且可操作以检测发射符号的标准何时跨越阈值并响应于跨越阈值来调整环路带宽。传输符号的标准可以是振幅信号或相位信号的函数的函数，并且可以是振幅信号，振幅信号的一阶导数，振幅信号的二阶导数，幅度的平方信号，幅度信号平方的导数，相位信号或相位信号的导数。

6. 发明申请

US20090325494A1 Transmitter PLL with Bandwidth on Demand 有权
标题翻译：发射器PLL带宽带宽
公开(公告)号：US20090325494A1
公开(公告)日：2009-12-31
申请号：US12412790
申请日：2009-03-27
申请人： Robert Bogdan Staszewski , Khurram Waheed , Sudheer K. Vemulapalli , Manouchehr Entezari , Imran Bashir
发明人： Robert Bogdan Staszewski , Khurram Waheed , Sudheer K. Vemulapalli , Manouchehr Entezari , Imran Bashir
IPC分类号： H04B7/00
CPC分类号： H03L7/085 , H03L7/093 , H03L7/0991 , H03L2207/50 , H04L27/361
摘要： An embodiment of the present invention provides transmitter having a phase locked loop that has a dynamically controllable loop bandwidth. A transmit modulator is coupled to the PLL for performing vector modulation in response to transmission symbols. Each transmission symbol comprises an amplitude signal and a phase signal. A controller is coupled to the PLL and to the transmit modulator and is operable to detect when a criteria of the transmission symbols crosses a threshold and to adjust loop bandwidth in response to crossing the threshold. The criteria of the transmission symbols may be a function of the amplitude signal or a function of the phase signal, and may be the amplitude signal, a first derivative of the amplitude signal, a second derivative of the amplitude signal, a square of the amplitude signal, a derivative of the amplitude signal squared, the phase signal, or a derivative of the phase signal.
摘要翻译：本发明的一个实施例提供具有锁相环的发射机，其具有动态可控的环路带宽。发射调制器耦合到PLL以响应于发射符号执行矢量调制。每个发送符号包括振幅信号和相位信号。控制器耦合到PLL和发射调制器，并且可操作以检测发射符号的标准何时跨越阈值并响应于跨越阈值来调整环路带宽。传输符号的标准可以是振幅信号或相位信号的函数的函数，并且可以是振幅信号，振幅信号的一阶导数，振幅信号的二阶导数，幅度的平方信号，幅度信号平方的导数，相位信号或相位信号的导数。

7. 发明申请

US20080315960A1 Digital Phase Locked Loop with Gear Shifting 有权
标题翻译：数字锁相环与齿轮换档
公开(公告)号：US20080315960A1
公开(公告)日：2008-12-25
申请号：US12137332
申请日：2008-06-11
申请人： Khurram Waheed , John Wallberg , Robert Bogdan Staszewski , Sudheer Vemulapalli
发明人： Khurram Waheed , John Wallberg , Robert Bogdan Staszewski , Sudheer Vemulapalli
IPC分类号： H03L7/099 , H03B5/12
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha-α) and an integral loop gain control having a programmable loop gain coefficient (rho-ρ). Alpha and rho are configured to be programmatically changed simultaneously and are selected such that the gain is changed and the phase margin remains substantially unchanged
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。连接可编程滤波器以接收相位误差样本并连接以提供具有对可控振荡器的增益和相位裕度的滤波输出。可编程滤波器包括具有可编程环路增益系数（α-α）的比例环路增益控制和具有可编程环路增益系数（rho-rho））的积分环路增益控制。 Alpha和rho被配置为同时编程地改变，并且被选择为使得增益改变并且相位裕度保持基本上不变

8. 发明授权

US07786913B2 Digital phase locked loop with dithering 有权
标题翻译：数字锁相环与抖动
公开(公告)号：US07786913B2
公开(公告)日：2010-08-31
申请号：US12114726
申请日：2008-05-02
申请人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
发明人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
IPC分类号： H03M3/00
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。抖动电路耦合到参考信号，并将短序列抖动信号注入到参考信号中，以便克服量化噪声，从而改进整数信道的RMS相位误差检测。

9. 发明授权

US07777576B2 Digital phase locked loop with gear shifting 有权
标题翻译：带变速的数字锁相环
公开(公告)号：US07777576B2
公开(公告)日：2010-08-17
申请号：US12137332
申请日：2008-06-11
申请人： Khurram Waheed , John Wallberg , Robert Bogdan Staszewski , Sudheer Vemulapalli
发明人： Khurram Waheed , John Wallberg , Robert Bogdan Staszewski , Sudheer Vemulapalli
IPC分类号： H03L7/093 , H03L7/16
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha—α) and an integral loop gain control having a programmable loop gain coefficient (rho—ρ). Alpha and rho are configured to be programmatically changed simultaneously and are selected such that the gain is changed and the phase margin remains substantially unchanged.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。连接可编程滤波器以接收相位误差样本并连接以提供具有对可控振荡器的增益和相位裕度的滤波输出。可编程滤波器包括具有可编程环路增益系数（α-α）的比例环路增益控制和具有可编程环路增益系数（rho- rgr）的积分环路增益控制。 Alpha和rho被配置为同时编程地改变，并且被选择为使得增益改变并且相位裕度保持基本上不变。

10. 发明授权

US07498890B2 Continuous reversible gear shifting mechanism 有权
标题翻译：连续可逆换档机构
公开(公告)号：US07498890B2
公开(公告)日：2009-03-03
申请号：US11551050
申请日：2006-10-19
申请人： John Wallberg , Robert Bogdan Staszewski , Khurram Waheed
发明人： John Wallberg , Robert Bogdan Staszewski , Khurram Waheed
IPC分类号： H03L7/085
CPC分类号： H03L7/093 , H03L7/0991 , H03L7/107 , H03L7/1075 , H03L7/1806
摘要： A novel gear shifting mechanism operative to adjust the loop gain of a phase locked loop (PLL) circuit in a continuous and reversible manner. The loop gain can be increased to widen the bandwidth of the loop and can also be decreased to narrow the loop bandwidth. The mechanism incorporates an α gear shift circuit, a ρ gear shift circuit and an optional IIR gear shift circuit. The α gear shift circuit comprises a infinite impulse response (IIR) filtering which enables hitless operation of the PLL loop at the occurrence of gear shift events. The α gear shift circuit comprises an accumulator whose output is multiplied by the gain value ρ. The invention enables multiple gear shifts in either positive or negative direction to be achieved by configuring the loop gain variables α and ρ which may be accomplished in software.
摘要翻译：一种新颖的换档机构，可以以连续和可逆的方式调节锁相环（PLL）电路的环路增益。可以增加环路增益以加宽环路的带宽，并且还可以减小环路带宽的窄度。该机构包括一个阿尔法换档电路，一个换档换档电路和一个可选的IIR换档电路。阿尔法换档电路包括无限脉冲响应（IIR）滤波，其能够在发生变速事件时实现PLL回路的无中断运行。阿尔法换档电路包括一个累加器，其输出乘以增益值rho。本发明通过配置可以在软件中实现的环路增益变量α和rho来实现正或负方向上的多个换档。

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