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1. 发明申请

US20130054217A1 CIRCUIT SIMULATION ACCELERATION USING MODEL CACHING 有权
标题翻译：使用模型缓存的电路模拟加速
公开(公告)号：US20130054217A1
公开(公告)日：2013-02-28
申请号：US13214827
申请日：2011-08-22
申请人： Kiran Kumar Gullapalli , Steven D. Hamm
发明人： Kiran Kumar Gullapalli , Steven D. Hamm
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A mechanism for improving speed of simulation of complex circuits that include transistors and other devices that share similar properties is provided. Circuit simulation speed is improved by efficiently identifying transistors and other devices having identical properties that share a same state at the time of interest in the simulation. Transistors and other devices are collected into groups having the same characteristics and topologies prior to simulation. Then during simulation, a determination is made as to whether a previously-evaluated transistor or device in the same group as a presently-being evaluated transistor or device has terminal input values that are the same, or nearly the same. If so, then output values of the previously-evaluated transistor or device are used in calculating the output values of the present transistor or device.
摘要翻译：提供了一种用于提高包括晶体管和其他具有类似特性的器件的复合电路的仿真速度的机制。通过有效地识别具有相同性质的晶体管和其他在仿真期间感兴趣的时间共享相同状态的装置来提高电路模拟速度。晶体管和其他器件在模拟之前被收集成具有相同特性和拓扑的组。然后在仿真期间，确定与当前评估的晶体管或器件相同的组中的先前评估的晶体管或器件是否具有相同或几乎相同的端子输入值。如果是这样，则在计算本晶体管或器件的输出值时使用先前评估的晶体管或器件的输出值。

2. 发明授权

US5799172A Method of simulating an integrated circuit 失效
标题翻译：模拟集成电路的方法
公开(公告)号：US5799172A
公开(公告)日：1998-08-25
申请号：US711638
申请日：1996-09-10
申请人： Kiran Kumar Gullapalli , Brian J. Mulvaney , Steven D. Hamm , Steven R. Beckerich
发明人： Kiran Kumar Gullapalli , Brian J. Mulvaney , Steven D. Hamm , Steven R. Beckerich
IPC分类号： G06F17/50 , G06G7/48
CPC分类号： G06F17/5036
摘要： A method and apparatus for simulating the design of an integrated circuit uses a processor (200). The processor (200) executes a simulator (540) from memory (280) to exercise a model (544). The data points (15-27) of an output signal are stored in a history data file (542). The techniques used to generate each of the data points (15-27) are also stored in the history data in file (542). The history data are then used to generate a converted output signal that has a uniform time scale. If the converted output signal requires the generation of a desired data point, then the approximation technique used to generate the following data point stored in the history data (542) is used.
摘要翻译：用于模拟集成电路的设计的方法和装置使用处理器（200）。处理器（200）从存储器（280）执行模拟器（540）以锻炼模型（544）。输出信号的数据点（15-27）存储在历史数据文件（542）中。用于生成每个数据点（15-27）的技术也被存储在文件（542）中的历史数据中。历史数据然后用于产生具有均匀时间尺度的转换的输出信号。如果转换的输出信号需要生成所需的数据点，则使用用于生成存储在历史数据（542）中的以下数据点的近似技术。

3. 发明授权

US08886508B2 Circuit simulation acceleration using model caching 有权
标题翻译：使用模型缓存的电路仿真加速
公开(公告)号：US08886508B2
公开(公告)日：2014-11-11
申请号：US13214827
申请日：2011-08-22
申请人： Kiran Kumar Gullapalli , Steven D. Hamm
发明人： Kiran Kumar Gullapalli , Steven D. Hamm
IPC分类号： G06F17/50 , G06F17/10 , G06F17/30
CPC分类号： G06F17/5022
摘要： A mechanism for improving speed of simulation of complex circuits that include transistors and other devices that share similar properties is provided. Circuit simulation speed is improved by efficiently identifying transistors and other devices having identical properties that share a same state at the time of interest in the simulation. Transistors and other devices are collected into groups having the same characteristics and topologies prior to simulation. Then during simulation, a determination is made as to whether a previously-evaluated transistor or device in the same group as a presently-being evaluated transistor or device has terminal input values that are the same, or nearly the same. If so, then output values of the previously-evaluated transistor or device are used in calculating the output values of the present transistor or device.
摘要翻译：提供了一种用于提高包括晶体管和其他具有类似特性的器件的复合电路的仿真速度的机制。通过有效地识别具有相同性质的晶体管和其他在仿真期间感兴趣的时间共享相同状态的装置来提高电路模拟速度。晶体管和其他器件在模拟之前被收集成具有相同特性和拓扑的组。然后在仿真期间，确定与当前评估的晶体管或器件相同的组中的先前评估的晶体管或器件是否具有相同或几乎相同的端子输入值。如果是这样，则在计算本晶体管或器件的输出值时使用先前评估的晶体管或器件的输出值。

4. 发明授权

US10229234B2 Method and apparatus to facilitate simulating a circuit connected to a multiport interconnect structure 有权
公开(公告)号：US10229234B2
公开(公告)日：2019-03-12
申请号：US14167671
申请日：2014-01-29
申请人： Kiran Kumar Gullapalli
发明人： Kiran Kumar Gullapalli
IPC分类号： G06F17/50
摘要： A method facilitates simulating a plurality of circuit elements connected to a multiport interconnect structure having a first set of ports. The method includes: receiving a first set of data that models electrical behavior of the first set of ports and a first portion of the plurality of circuit elements; determining a first subset of the first data, which models electrical behavior of a set of exposed ports of the first set of ports, and a second subset of the first data, which models electrical behavior of a set of non-exposed ports of the first set of ports and the first portion of the plurality of circuit elements; and combining the second subset of the first data into the first subset of the first data to generate a second set of data that models electrical behavior of a second interconnect structure having fewer ports than the multiport interconnect structure.

5. 发明申请

US20150213171A1 Method and Apparatus to Facilitate Simulating a Circuit Connected to a Multiport Interconnect Structure 审中-公开
标题翻译：便于模拟连接到多端口互连结构的电路的方法和装置
公开(公告)号：US20150213171A1
公开(公告)日：2015-07-30
申请号：US14167671
申请日：2014-01-29
申请人： Kiran Kumar Gullapalli
发明人： Kiran Kumar Gullapalli
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method facilitates simulating a plurality of circuit elements connected to a multiport interconnect structure having a first set of ports. The method includes: receiving a first set of data that models electrical behavior of the first set of ports and a first portion of the plurality of circuit elements; determining a first subset of the first data, which models electrical behavior of a set of exposed ports of the first set of ports, and a second subset of the first data, which models electrical behavior of a set of non-exposed ports of the first set of ports and the first portion of the plurality of circuit elements; and combining the second subset of the first data into the first subset of the first data to generate a second set of data that models electrical behavior of a second interconnect structure having fewer ports than the multiport interconnect structure.
摘要翻译：一种方法有助于模拟连接到具有第一组端口的多端口互连结构的多个电路元件。该方法包括：接收对第一组端口的电气行为和多个电路元件的第一部分进行建模的第一组数据; 确定所述第一数据的第一子集，其对所述第一组端口的一组暴露的端口的电气行为和所述第一数据的第二子集进行建模，所述第一子集对所述第一数据的一组非暴露端口的电行为进行建模，一组端口和多个电路元件的第一部分; 以及将所述第一数据的第二子集合到所述第一数据的所述第一子集中，以生成第二组数据，所述第二组数据对具有比所述多端口互连结构更少的端口的第二互连结构进行建模。

6. 发明授权

US5687355A Apparatus and method for modeling a graded channel transistor 失效
标题翻译：用于对分级通道晶体管进行建模的装置和方法
公开(公告)号：US5687355A
公开(公告)日：1997-11-11
申请号：US517046
申请日：1995-08-21
申请人： Kuntal Joardar , Kiran Kumar Gullapalli
发明人： Kuntal Joardar , Kiran Kumar Gullapalli
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5036
摘要： The present invention generates a model of a graded channel transistor having at least two channel portions of differing doping concentrations. The present invention assumes a uniform doping concentration of each channel portion. Each of the channel portions is modeled using a standard transistor model (100, 120) with junction voltages (64) resulting between the transistor models. The junction voltages (64) are determined to be at a level such that the channel currents of the transistor models (60, 62) are equal. Once the junction voltages (64) are determined, the parameters of the transistor models (60, 62) are determined. Once the transistor models (60, 62) are determined, the models are combined to produce a composite transistor model (70) for the transistor using standard circuit reduction techniques. The composite model produced is scalable with respect to geometry, is continuous, and is differentiable. Steps are also disclosed for manufacturing integrated circuits using the modeling techniques of the present invention.
摘要翻译：本发明产生具有不同掺杂浓度的至少两个沟道部分的渐变沟道晶体管的模型。本发明假设每个通道部分的掺杂浓度均匀。使用具有在晶体管模型之间产生的结电压（64）的标准晶体管模型（100,120）来对每个沟道部分进行建模。结电压（64）被确定为使得晶体管型号（60,62）的沟道电流相等的电平。一旦确定了结电压（64），就确定晶体管模型（60,62）的参数。一旦确定了晶体管模型（60,62），就使用标准电路还原技术将模型组合以产生用于晶体管的复合晶体管模型（70）。生成的复合模型相对于几何是可扩展的，是连续的，并且是可微分的。还公开了使用本发明的建模技术制造集成电路的步骤。

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