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1. 发明授权

US08886508B2 Circuit simulation acceleration using model caching 有权
标题翻译：使用模型缓存的电路仿真加速
公开(公告)号：US08886508B2
公开(公告)日：2014-11-11
申请号：US13214827
申请日：2011-08-22
申请人： Kiran Kumar Gullapalli , Steven D. Hamm
发明人： Kiran Kumar Gullapalli , Steven D. Hamm
IPC分类号： G06F17/50 , G06F17/10 , G06F17/30
CPC分类号： G06F17/5022
摘要： A mechanism for improving speed of simulation of complex circuits that include transistors and other devices that share similar properties is provided. Circuit simulation speed is improved by efficiently identifying transistors and other devices having identical properties that share a same state at the time of interest in the simulation. Transistors and other devices are collected into groups having the same characteristics and topologies prior to simulation. Then during simulation, a determination is made as to whether a previously-evaluated transistor or device in the same group as a presently-being evaluated transistor or device has terminal input values that are the same, or nearly the same. If so, then output values of the previously-evaluated transistor or device are used in calculating the output values of the present transistor or device.
摘要翻译：提供了一种用于提高包括晶体管和其他具有类似特性的器件的复合电路的仿真速度的机制。通过有效地识别具有相同性质的晶体管和其他在仿真期间感兴趣的时间共享相同状态的装置来提高电路模拟速度。晶体管和其他器件在模拟之前被收集成具有相同特性和拓扑的组。然后在仿真期间，确定与当前评估的晶体管或器件相同的组中的先前评估的晶体管或器件是否具有相同或几乎相同的端子输入值。如果是这样，则在计算本晶体管或器件的输出值时使用先前评估的晶体管或器件的输出值。

2. 发明申请

US20130054217A1 CIRCUIT SIMULATION ACCELERATION USING MODEL CACHING 有权
标题翻译：使用模型缓存的电路模拟加速
公开(公告)号：US20130054217A1
公开(公告)日：2013-02-28
申请号：US13214827
申请日：2011-08-22
申请人： Kiran Kumar Gullapalli , Steven D. Hamm
发明人： Kiran Kumar Gullapalli , Steven D. Hamm
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A mechanism for improving speed of simulation of complex circuits that include transistors and other devices that share similar properties is provided. Circuit simulation speed is improved by efficiently identifying transistors and other devices having identical properties that share a same state at the time of interest in the simulation. Transistors and other devices are collected into groups having the same characteristics and topologies prior to simulation. Then during simulation, a determination is made as to whether a previously-evaluated transistor or device in the same group as a presently-being evaluated transistor or device has terminal input values that are the same, or nearly the same. If so, then output values of the previously-evaluated transistor or device are used in calculating the output values of the present transistor or device.
摘要翻译：提供了一种用于提高包括晶体管和其他具有类似特性的器件的复合电路的仿真速度的机制。通过有效地识别具有相同性质的晶体管和其他在仿真期间感兴趣的时间共享相同状态的装置来提高电路模拟速度。晶体管和其他器件在模拟之前被收集成具有相同特性和拓扑的组。然后在仿真期间，确定与当前评估的晶体管或器件相同的组中的先前评估的晶体管或器件是否具有相同或几乎相同的端子输入值。如果是这样，则在计算本晶体管或器件的输出值时使用先前评估的晶体管或器件的输出值。

3. 发明授权

US5799172A Method of simulating an integrated circuit 失效
标题翻译：模拟集成电路的方法
公开(公告)号：US5799172A
公开(公告)日：1998-08-25
申请号：US711638
申请日：1996-09-10
申请人： Kiran Kumar Gullapalli , Brian J. Mulvaney , Steven D. Hamm , Steven R. Beckerich
发明人： Kiran Kumar Gullapalli , Brian J. Mulvaney , Steven D. Hamm , Steven R. Beckerich
IPC分类号： G06F17/50 , G06G7/48
CPC分类号： G06F17/5036
摘要： A method and apparatus for simulating the design of an integrated circuit uses a processor (200). The processor (200) executes a simulator (540) from memory (280) to exercise a model (544). The data points (15-27) of an output signal are stored in a history data file (542). The techniques used to generate each of the data points (15-27) are also stored in the history data in file (542). The history data are then used to generate a converted output signal that has a uniform time scale. If the converted output signal requires the generation of a desired data point, then the approximation technique used to generate the following data point stored in the history data (542) is used.
摘要翻译：用于模拟集成电路的设计的方法和装置使用处理器（200）。处理器（200）从存储器（280）执行模拟器（540）以锻炼模型（544）。输出信号的数据点（15-27）存储在历史数据文件（542）中。用于生成每个数据点（15-27）的技术也被存储在文件（542）中的历史数据中。历史数据然后用于产生具有均匀时间尺度的转换的输出信号。如果转换的输出信号需要生成所需的数据点，则使用用于生成存储在历史数据（542）中的以下数据点的近似技术。

4. 发明授权

US09135383B2 Table model circuit simulation acceleration using model caching 有权
标题翻译：表模型电路仿真加速采用模型缓存
公开(公告)号：US09135383B2
公开(公告)日：2015-09-15
申请号：US13678789
申请日：2012-11-16
申请人： Kiran Gullapalli , Steven D. Hamm
发明人： Kiran Gullapalli , Steven D. Hamm
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A mechanism for improving speed of table model-based simulation of complex circuits that include transistors and other devices that share similar properties is provided. Circuit simulation speed is improved by efficiently identifying transistors and other devices having substantially the same properties that share a same state at the time of interest in the simulation. Transistors and other devices are collected into groups having the same characteristics and topologies prior to simulation. Then during simulation, a determination is made as to whether a previously-evaluated transistor or device in the same group as a presently-being evaluated transistor or device has terminal input values that are the same, or nearly the same. If so, a cache lookup is performed to determine table model solution values for the previously-evaluated transistor or device, and those values are used to determine exact output values per the table model of the presently being evaluated transistor or device.
摘要翻译：提供了一种用于提高包含晶体管和其他具有类似属性的设备的复杂电路的基于表模型的仿真的速度的机制。通过有效地识别晶体管和具有在模拟中感兴趣时具有相同状态的具有基本上相同性质的其它器件来提高电路模拟速度。晶体管和其他器件在模拟之前被收集成具有相同特性和拓扑的组。然后在仿真期间，确定与当前评估的晶体管或器件相同的组中的先前评估的晶体管或器件是否具有相同或几乎相同的端子输入值。如果是这样，则执行高速缓存查找以确定先前评估的晶体管或器件的表模型解值，并且这些值用于确定当前正在评估的晶体管或器件的表模型的精确输出值。

5. 发明申请

US20140142903A1 TABLE MODEL CIRCUIT SIMULATION ACCELERATION USING MODEL CACHING 有权
标题翻译：使用模型缓存的表模型电路仿真加速
公开(公告)号：US20140142903A1
公开(公告)日：2014-05-22
申请号：US13678789
申请日：2012-11-16
申请人： Kiran Gullapalli , Steven D. Hamm
发明人： Kiran Gullapalli , Steven D. Hamm
IPC分类号： G06F17/10
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A mechanism for improving speed of table model-based simulation of complex circuits that include transistors and other devices that share similar properties is provided. Circuit simulation speed is improved by efficiently identifying transistors and other devices having substantially the same properties that share a same state at the time of interest in the simulation. Transistors and other devices are collected into groups having the same characteristics and topologies prior to simulation. Then during simulation, a determination is made as to whether a previously-evaluated transistor or device in the same group as a presently-being evaluated transistor or device has terminal input values that are the same, or nearly the same. If so, a cache lookup is performed to determine table model solution values for the previously-evaluated transistor or device, and those values are used to determine exact output values per the table model of the presently being evaluated transistor or device.
摘要翻译：提供了一种用于提高包含晶体管和其他具有类似属性的设备的复杂电路的基于表模型的仿真的速度的机制。通过有效地识别晶体管和具有在模拟中感兴趣时具有相同状态的具有基本上相同性质的其它器件来提高电路模拟速度。晶体管和其他器件在模拟之前被收集成具有相同特性和拓扑的组。然后在仿真期间，确定与当前评估的晶体管或器件相同的组中的先前评估的晶体管或器件是否具有相同或几乎相同的端子输入值。如果是这样，则执行高速缓存查找以确定先前评估的晶体管或器件的表模型解值，并且这些值用于确定当前正在评估的晶体管或器件的表模型的精确输出值。

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