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1. 发明授权

US09054660B1 Amplifying system 有权
标题翻译：放大系统
公开(公告)号：US09054660B1
公开(公告)日：2015-06-09
申请号：US14152515
申请日：2014-01-10
申请人： Kirubakaran Ramalingam , Rabeesh Vadassery Gopinathan , Kaushal Kumar Jha , Damien J. McCartney
发明人： Kirubakaran Ramalingam , Rabeesh Vadassery Gopinathan , Kaushal Kumar Jha , Damien J. McCartney
IPC分类号： H03F1/48 , H03F3/45 , H03G3/00 , H03M1/66 , H03M1/70 , H03G3/30
CPC分类号： H03G3/001 , H03G1/0088
摘要： A digital-to-analog conversion system includes a digital-to-analog converter and an output stage for converting an output signal of the digital-to-analog converter into a voltage range. The output stage includes a first amplifier including a first input for receiving the output signal of the digital-to-analog converter, a first resistance element coupled between a second input and an output of the first amplifier, a second resistance element coupled between the second input of the first amplifier and a ground reference, and a third resistance element switchably coupled from the second input of the first amplifier to an offset voltage.
摘要翻译：数模转换系统包括数模转换器和用于将数模转换器的输出信号转换成电压范围的输出级。输出级包括第一放大器，其包括用于接收数模转换器的输出信号的第一输入端，耦合在第一放大器的第二输入端和第二输出端之间的第一电阻元件，第一放大器的输入和接地基准，以及从第一放大器的第二输入端切换耦合到偏移电压的第三电阻元件。

2. 发明授权

US07982581B2 Digital potentiometer architecture with multiple string arrays allowing for independent calibration in rheostat mode 有权
标题翻译：具有多个串联阵列的数字电位器架构，允许在变阻器模式下进行独立校准
公开(公告)号：US07982581B2
公开(公告)日：2011-07-19
申请号：US12367243
申请日：2009-02-06
申请人： Kaushal Kumar Jha , Mrinmay Talegaonkar , Kirubakaran Ramalingam , Bhargav Vyas
发明人： Kaushal Kumar Jha , Mrinmay Talegaonkar , Kirubakaran Ramalingam , Bhargav Vyas
IPC分类号： H01C10/30
CPC分类号： H03H7/24
摘要： Digital potentiometer architecture is disclosed, composing of an integrated circuit containing multiple string arrays, each having a plurality of switching devices and an array of resistors. The insertion of an additional string array between the input terminals and the wiper, allows for the disconnection of a common string array and for the independent calibration of the resistance between each input terminal and the wiper.
摘要翻译：公开了一种数字电位计架构，其由包含多个串组的集成电路组成，每个具有多个开关器件和一组电阻器。在输入端子和擦拭器之间插入附加的串阵列允许断开公共串阵列并且用于独立校准每个输入端子和擦拭器之间的电阻。

3. 发明申请

US20090273497A1 METHOD AND APPARATUS FOR CALIBRATING AN RDAC FOR END-TO-END TOLERANCE CORRECTION OF OUTPUT RESISTANCE 有权
标题翻译：用于校准RDAC以实现输出电阻端到端测量校正的方法和装置
公开(公告)号：US20090273497A1
公开(公告)日：2009-11-05
申请号：US12113946
申请日：2008-05-02
申请人： DINESH JAIN , Kaushal Kumar Jha
发明人： DINESH JAIN , Kaushal Kumar Jha
IPC分类号： H03M1/10 , H03M1/66
CPC分类号： H03M1/1028 , H03M1/682 , H03M1/765
摘要： A system and method for calibrating an RDAC to obtain an expected resistance are disclosed. In one embodiment, a method of obtaining an expected resistance from an RDAC circuit includes receiving a digital signal comprising a digital code by an on-chip calibration code engine, automatically deriving a calibrated digital code based on resistance versus digital code characteristic curves of an expected RDAC and the RDAC associated with the calibration code engine, and inputting the calibrated digital code into the RDAC associated with the calibration code engine to obtain an expected resistance. The method also includes forming the resistance versus digital code characteristic curves of the expected RDAC and the RDAC, computing a gain error and an offset error using the formed resistance versus digital code characteristic curves of the RDAC and the expected RDAC and storing the gain error and the offset error in a non-volatile/volatile RDAC memory.
摘要翻译：公开了一种用于校准RDAC以获得预期电阻的系统和方法。在一个实施例中，从RDAC电路获得预期电阻的方法包括通过片上校准代码引擎接收包括数字代码的数字信号，基于期望的电阻与数字代码特性曲线自动导出经校准的数字代码 RDAC和与校准代码引擎相关联的RDAC，以及将校准的数字代码输入到与校准代码引擎相关联的RDAC中以获得期望的阻力。该方法还包括形成预期RDAC和RDAC的电阻与数字码特性曲线，使用RDAC和预期RDAC的形成的电阻与数字码特性曲线计算增益误差和偏移误差，并存储增益误差和非易失性/易失性RDAC存储器中的偏移误差。

4. 发明授权

US08284014B2 Digital potentiometer with independent control over both resistive arms 有权
标题翻译：数字电位器可独立控制两个电阻臂
公开(公告)号：US08284014B2
公开(公告)日：2012-10-09
申请号：US12861103
申请日：2010-08-23
申请人： Kaushal Kumar Jha
发明人： Kaushal Kumar Jha
IPC分类号： H01C10/30
CPC分类号： H01C10/30
摘要： A digital potentiometer includes a circuit containing multiple string arrays, each having a plurality of switching devices connected to an array of resistors. Each input terminal receives a separate digital input code enabling the resistance of one of the arms to be varied without changing the other.
摘要翻译：一个数字电位计包括一个包含多个串阵列的电路，每个阵列具有连接到电阻阵列的多个开关装置。每个输入端子接收单独的数字输入代码，使得能够改变一个臂的电阻而不改变另一个。

5. 发明授权

US07688240B2 Method and apparatus for calibrating an RDAC for end-to-end tolerance correction of output resistance 有权
标题翻译：校准RDAC的输出电阻的端到端容限校正的方法和装置
公开(公告)号：US07688240B2
公开(公告)日：2010-03-30
申请号：US12113946
申请日：2008-05-02
申请人： Dinesh Jain , Kaushal Kumar Jha
发明人： Dinesh Jain , Kaushal Kumar Jha
IPC分类号： H03M1/10
CPC分类号： H03M1/1028 , H03M1/682 , H03M1/765
摘要： A system and method for calibrating an RDAC to obtain an expected resistance are disclosed. In one embodiment, a method of obtaining an expected resistance from an RDAC circuit includes receiving a digital signal comprising a digital code by an on-chip calibration code engine, automatically deriving a calibrated digital code based on resistance versus digital code characteristic curves of an expected RDAC and the RDAC associated with the calibration code engine, and inputting the calibrated digital code into the RDAC associated with the calibration code engine to obtain an expected resistance. The method also includes forming the resistance versus digital code characteristic curves of the expected RDAC and the RDAC, computing a gain error and an offset error using the formed resistance versus digital code characteristic curves of the RDAC and the expected RDAC and storing the gain error and the offset error in a non-volatile/volatile RDAC memory.
摘要翻译：公开了一种用于校准RDAC以获得预期电阻的系统和方法。在一个实施例中，从RDAC电路获得预期电阻的方法包括通过片上校准代码引擎接收包括数字代码的数字信号，基于期望的电阻与数字代码特性曲线自动导出经校准的数字代码 RDAC和与校准代码引擎相关联的RDAC，以及将校准的数字代码输入到与校准代码引擎相关联的RDAC中以获得期望的阻力。该方法还包括形成预期RDAC和RDAC的电阻与数字码特性曲线，使用RDAC和预期RDAC的形成的电阻与数字码特性曲线计算增益误差和偏移误差，并存储增益误差和非易失性/易失性RDAC存储器中的偏移误差。

6. 发明授权

US06914547B1 Triple resistor string DAC architecture 有权
标题翻译：三电阻串DAC架构
公开(公告)号：US06914547B1
公开(公告)日：2005-07-05
申请号：US10838806
申请日：2004-05-04
申请人： Prem S Swaroop , Arindam Raychaudhuri , Kaushal Kumar Jha
发明人： Prem S Swaroop , Arindam Raychaudhuri , Kaushal Kumar Jha
IPC分类号： H03M1/66 , H03M1/76 , H03M1/78
CPC分类号： H03M1/682 , H03M1/765
摘要： A technique to provide a higher resolution DAC architecture for converting an N-bit digital word to a corresponding analog voltage signal without increasing chip area and switching capacitance. In one example embodiment, this is accomplished by using a triple string converter. In the triple string converter, a triple switching tree is coupled to a triple resistor string and to an analog output. Each switching tree includes a plurality of switches and each resistor string includes a plurality of corresponding resistors. A logic decoder coupled to the triple switching tree receives an N-bit digital word and generates a digital signal. The plurality of switches in each switching tree is substantially simultaneously controlled by the digital signal to output a range of corresponding analog voltage signals when the triple resistor string is connected across a voltage supply.
摘要翻译：提供用于将N位数字字转换为相应的模拟电压信号而不增加芯片面积和开关电容的更高分辨率DAC架构的技术。在一个示例性实施例中，这通过使用三串转换器来实现。在三串转换器中，三重切换树耦合到三电阻串和模拟输出。每个开关树包括多个开关，每个电阻串包括多个对应的电阻器。耦合到三重切换树的逻辑解码器接收N位数字字并产生数字信号。当三电阻串跨越电压源连接时，每个开关树中的多个开关基本上同时由数字信号控制，以输出相应模拟电压信号的范围。

7. 发明授权

US6134686A Technique to detect drive strength of input pin 失效
标题翻译：检测输入引脚的驱动强度的技术
公开(公告)号：US6134686A
公开(公告)日：2000-10-17
申请号：US86870
申请日：1998-05-29
申请人： Kaushal Kumar Jha
发明人： Kaushal Kumar Jha
IPC分类号： G01R31/30 , G01R31/28
CPC分类号： G01R31/3004 , G01R31/31701
摘要： A method and apparatus comprising (i) a first circuit that may be configured to generate a first and second pulse in response to a reset signal, (ii) a latch circuit that may be configured to generate a first and second latch output in response to (a) the first and second pulses, (b) the reset signal and (c) an input signal and (iii) a third circuit that may be configured to generate a detect output in response to the first and second latch outputs. The detect output may be implemented as a trigger signal having an enabled state indicating a floating voltage is present on the input signal. The first and second latch outputs may be used to indicate the drive strength of the input signal. The enabled state of the detect output may have a floating state other than a standard logic "1" or logic "0".
摘要翻译：一种方法和装置，包括：（i）第一电路，其可以被配置为响应于复位信号产生第一和第二脉冲;（ii）锁存电路，其可被配置为响应于所述锁存电路产生第一和第二锁存器输出（a）第一和第二脉冲，（b）复位信号和（c）输入信号，以及（iii）可被配置为响应于第一和第二锁存输出而产生检测输出的第三电路。检测输出可以被实现为具有指示浮动电压存在于输入信号上的使能状态的触发信号。第一和第二锁存器输出可以用于指示输入信号的驱动强度。检测输出的使能状态可以具有除了标准逻辑“1”或逻辑“0”之外的浮动状态。

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