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1. 发明申请

US20080029764A1 Capacitor, method of producing the same, semiconductor device, and liquid crystal display device 有权
标题翻译：电容器及其制造方法，半导体器件和液晶显示装置
公开(公告)号：US20080029764A1
公开(公告)日：2008-02-07
申请号：US11880551
申请日：2007-07-23
申请人： Kiwamu Adachi , Satoshi Horiuchi
发明人： Kiwamu Adachi , Satoshi Horiuchi
IPC分类号： H01L29/04 , H01L21/20 , H01L29/00
CPC分类号： H01G4/10 , G02F1/136213 , H01G4/1254 , H01G4/20 , H01G4/33 , H01L28/40 , H01L28/56
摘要： A capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially stacked. The dielectric layer has a stacked layer structure including a predetermined number of hafnium oxide sublayers and predetermined number of tantalum oxide sublayers. The number, materials, and thicknesses of the sublayers are determined so that the thickness ratio has a range in which, in voltage-leakage current characteristics showing the relationship between the voltage between the first and second electrodes and the leakage current, a start voltage at which the slope of an increase in the current starts to discontinuously increase satisfies an electric field strength of 3 [MV/cm] or more when the ratio of the total thickness of the predetermined number of tantalum oxide sublayers to the total thickness of the dielectric layer is varied, and the thickness ratio is within the range such that the start voltage is within the range.
摘要翻译：电容器包括依次层叠的第一电极，电介质层和第二电极。电介质层具有包含规定数量的氧化铪层和预定数量的氧化钽层的堆叠层结构。确定子层的数量，材料和厚度，使得厚度比具有这样的范围，其中，在表示第一和第二电极之间的电压与漏电流之间的关系的电压 - 漏电流特性中，当电流增加的斜率开始不连续地增加时，当预定数量的氧化钽层的总厚度与介电层的总厚度的比例达到3 [MV / cm]以上时的电场强度变化，厚度比在起始电压在该范围内的范围内。

2. 发明授权

US08237242B2 Capacitor, method of producing the same, semiconductor device, and liquid crystal display device 有权
标题翻译：电容器及其制造方法，半导体器件和液晶显示装置
公开(公告)号：US08237242B2
公开(公告)日：2012-08-07
申请号：US11880551
申请日：2007-07-23
申请人： Kiwamu Adachi , Satoshi Horiuchi
发明人： Kiwamu Adachi , Satoshi Horiuchi
IPC分类号： H01L29/92
CPC分类号： H01G4/10 , G02F1/136213 , H01G4/1254 , H01G4/20 , H01G4/33 , H01L28/40 , H01L28/56
摘要： A capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially stacked. The dielectric layer has a stacked layer structure including a predetermined number of hafnium oxide sublayers and predetermined number of tantalum oxide sublayers. The number, materials, and thicknesses of the sublayers are determined so that the thickness ratio has a range in which, in voltage-leakage current characteristics showing the relationship between the voltage between the first and second electrodes and the leakage current, a start voltage at which the slope of an increase in the current starts to discontinuously increase satisfies an electric field strength of 3 [MV/cm] or more when the ratio of the total thickness of the predetermined number of tantalum oxide sublayers to the total thickness of the dielectric layer is varied, and the thickness ratio is within the range such that the start voltage is within the range.
摘要翻译：电容器包括依次层叠的第一电极，电介质层和第二电极。电介质层具有包含规定数量的氧化铪层和预定数量的氧化钽层的堆叠层结构。确定子层的数量，材料和厚度，使得厚度比具有这样的范围，其中，在表示第一和第二电极之间的电压与漏电流之间的关系的电压 - 漏电流特性中，当电流增加的斜率开始不连续地增加时，当预定数量的氧化钽层的总厚度与介电层的总厚度的比例达到3 [MV / cm]以上时的电场强度变化，厚度比在起始电压在该范围内的范围内。

3. 发明授权

US06916747B2 Method of manufacturing amorphous metal oxide film and methods of manufacturing capacitance element having amorphous metal oxide film and semiconductor device 失效
标题翻译：制造非晶金属氧化物膜的方法和制造具有非晶金属氧化物膜的电容元件和半导体器件的方法
公开(公告)号：US06916747B2
公开(公告)日：2005-07-12
申请号：US10395389
申请日：2003-03-25
申请人： Kiwamu Adachi , Satoshi Horiuchi , Tetsuya Yukimoto
发明人： Kiwamu Adachi , Satoshi Horiuchi , Tetsuya Yukimoto
IPC分类号： C23C16/40 , C23C16/56 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/301 , H01L21/461
CPC分类号： H01L21/31604 , C23C16/405 , C23C16/56 , H01L28/40
摘要： A film deposition process for depositing an amorphous metal oxide film, for example, an amorphous tantalum oxide film, and a film treatment process for improving the film quality of the amorphous tantalum oxide film in the state in which an amorphous state of the amorphous metal oxide film is maintained by a high-density plasma radiation treatment based upon ion and radical reactions, and which contains at least oxygen at an ion current density higher than 5 mA/cm2 are carried out, whereby a low-temperature treatment in the whole process is made possible. In addition, since the amorphous metal oxide film, which is excellent in film quality, can be deposited, the amorphous metal oxide film can be made high in reliability and can be produced inexpensively. The amorphous tantalum oxide film, which is excellent in film quality, can be manufactured inexpensively by a low-temperature treatment. Also, when a capacitance element having an amorphous metal oxide film and a semiconductor device are manufactured, the amorphous metal oxide film, which is excellent in film quality, can be deposited by a low-temperature treatment and a highly-reliable capacitance element and semiconductor device can be manufactured.
摘要翻译：用于沉积非晶态金属氧化物膜的成膜方法，例如非晶形氧化钽膜，以及用于提高非晶态氧化钽膜的非晶状态的非晶态氧化钽膜的膜质量的膜处理方法通过基于离子和自由基反应的高密度等离子体辐射处理来维持膜，并且其至少包含离子电流密度高于5mA / cm 2的氧，由此低整个过程中的温度处理成为可能。另外，由于可以沉积膜质量优异的非晶金属氧化物膜，所以可以使非晶金属氧化物膜的可靠性高，并且可以廉价地制造。可以通过低温处理廉价地制造膜质量优异的无定形氧化钽膜。此外，当制造具有非晶金属氧化物膜和半导体器件的电容元件时，可以通过低温处理和高可靠性的电容元件和半导体来沉积膜质量优异的非晶态金属氧化物膜装置可以制造。

4. 发明授权

US07666793B2 Method of manufacturing amorphous metal oxide film and methods of manufacturing capacitance element having amorphous metal oxide film and semiconductor device 失效
标题翻译：制造非晶金属氧化物膜的方法和制造具有非晶金属氧化物膜的电容元件和半导体器件的方法
公开(公告)号：US07666793B2
公开(公告)日：2010-02-23
申请号：US10998759
申请日：2004-11-30
申请人： Kiwamu Adachi , Satoshi Horiuchi , Tetsuya Yukimoto
发明人： Kiwamu Adachi , Satoshi Horiuchi , Tetsuya Yukimoto
IPC分类号： H01L21/00
CPC分类号： H01L21/31604 , C23C16/405 , C23C16/56 , H01L28/40
摘要： A film deposition process for depositing an amorphous metal oxide film, for example, an amorphous tantalum oxide film and a film treatment process for improving film quality of the amorphous tantalum oxide film in the state in which an amorphous state of the amorphous metal oxide film is being maintained by a high-density plasma radiation treatment based upon ion and radical reactions and which contains at least oxygen at an ion current density higher than 5 mA/cm2 are carried out, whereby a low-temperature treatment in the whole process is made possible. In addition, since the amorphous metal oxide film, which is excellent in film quality, can be deposited, the amorphous metal oxide film can be made high in reliability and can be produced inexpensively. The amorphous tantalum oxide film which is excellent in film quality can be manufactured inexpensively by a low-temperature treatment. Also, when a capacitance element having an amorphous metal oxide film and a semiconductor device are manufactured, the amorphous metal oxide film which is excellent in film quality can be deposited by a low-temperature treatment and highly-reliable capacitance element and semiconductor device can be manufactured.
摘要翻译：用于沉积非晶态金属氧化物膜的成膜方法，例如非晶态氧化钽膜和用于提高非晶态氧化金属膜的非晶态的状态下的非晶态氧化钽膜的膜质量的膜处理方法通过基于离子和自由基反应的高密度等离子体辐射处理进行维持，并且至少含有离子电流密度高于5mA / cm 2的氧，从而使整个过程中的低温处理成为可能。另外，由于可以沉积膜质量优异的非晶金属氧化物膜，所以可以使非晶金属氧化物膜的可靠性高，并且可以廉价地制造。可以通过低温处理廉价地制造膜质量优异的无定形氧化钽膜。此外，当制造具有非晶金属氧化物膜和半导体器件的电容元件时，可以通过低温处理和高度可靠的电容元件来沉积膜质量优异的非晶金属氧化物膜，并且半导体器件可以制造。

5. 发明申请

US20050095850A1 Method of manufacturing amorphous metal oxide film and methods of manufacturing capacitance element having amorphous metal oxide film and semiconductor device 失效
标题翻译：制造非晶金属氧化物膜的方法和制造具有非晶金属氧化物膜的电容元件和半导体器件的方法
公开(公告)号：US20050095850A1
公开(公告)日：2005-05-05
申请号：US10998759
申请日：2004-11-30
申请人： Kiwamu Adachi , Satoshi Horiuchi , Tetsuya Yukimoto
发明人： Kiwamu Adachi , Satoshi Horiuchi , Tetsuya Yukimoto
IPC分类号： C23C16/40 , C23C16/56 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/44
CPC分类号： H01L21/31604 , C23C16/405 , C23C16/56 , H01L28/40
摘要： A film deposition process for depositing an amorphous metal oxide film, for example, an amorphous tantalum oxide film and a film treatment process for improving film quality of the amorphous tantalum oxide film in the state in which an amorphous state of the amorphous metal oxide film is being maintained by a high-density plasma radiation treatment based upon ion and radical reactions and which contains at least oxygen at an ion current density higher than 5 mA/cm2 are carried out, whereby a low-temperature treatment in the whole process is made possible. In addition, since the amorphous metal oxide film, which is excellent in film quality, can be deposited, the amorphous metal oxide film can be made high in reliability and can be produced inexpensively. The amorphous tantalum oxide film which is excellent in film quality can be manufactured inexpensively by a low-temperature treatment. Also, when a capacitance element having an amorphous metal oxide film and a semiconductor device are manufactured, the amorphous metal oxide film which is excellent in film quality can be deposited by a low-temperature treatment and highly-reliable capacitance element and semiconductor device can be manufactured.
摘要翻译：用于沉积非晶态金属氧化物膜的成膜方法，例如非晶态氧化钽膜和用于提高非晶态氧化金属膜的非晶态的状态下的非晶态氧化钽膜的膜质量的膜处理方法通过基于离子和自由基反应的高密度等离子体辐射处理进行维持，并且至少含有离子电流密度高于5mA / cm 2的氧，由此低温整个过程中的治疗成为可能。另外，由于可以沉积膜质量优异的非晶金属氧化物膜，所以可以使非晶金属氧化物膜的可靠性高，并且可以廉价地制造。可以通过低温处理廉价地制造膜质量优异的无定形氧化钽膜。此外，当制造具有非晶金属氧化物膜和半导体器件的电容元件时，可以通过低温处理和高度可靠的电容元件来沉积膜质量优异的非晶金属氧化物膜，并且半导体器件可以制造。

6. 发明授权

US08536463B2 Printed-circuit board and manufacturing method thereof 失效
标题翻译：印刷电路板及其制造方法
公开(公告)号：US08536463B2
公开(公告)日：2013-09-17
申请号：US12923997
申请日：2010-10-20
申请人： Mitsuharu Shoji , Kiwamu Adachi
发明人： Mitsuharu Shoji , Kiwamu Adachi
IPC分类号： H05K3/02 , H05K3/10 , H05K1/16
CPC分类号： H05K1/162 , H05K2201/09509 , H05K2201/09763 , H05K2203/125
摘要： A method for manufacturing a printed-circuit board including: a capacitive element forming step of embedding a capacitive element in a substrate resin layer inside a substrate that includes a plurality of wiring layers laminated with the substrate resin layer interposed in between, the capacitive element forming step including forming a lower electrode using a conductive layer on one of the plurality of wiring layers, or using one of the plurality of wiring layers; forming a crystalline metal oxide-containing capacitor dielectric film at a temperature at or below a heat-resistant temperature of the substrate resin layer, and at or above room temperature; and forming an upper electrode on an upper surface of the capacitor dielectric film on the side opposite to the lower electrode.
摘要翻译：一种印刷电路板的制造方法，其特征在于，包括：电容元件形成步骤，将电容元件嵌入到基板内部的基板树脂层内，所述基板包括与介于其间的基板树脂层层叠的多个布线层，所述电容元件形成包括在所述多个布线层之一上使用导电层形成下电极，或者使用所述多个布线层中的一个布线层; 在等于或低于衬底树脂层的耐热温度或低于室温的温度下形成含结晶金属氧化物的电容器电介质膜; 以及在所述电容器电介质膜的与所述下电极相反的一侧的上表面上形成上电极。

7. 发明申请

US20120307469A1 MULTILAYER WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE 有权
标题翻译：多层接线板及其制造方法及半导体器件
公开(公告)号：US20120307469A1
公开(公告)日：2012-12-06
申请号：US13480925
申请日：2012-05-25
申请人： Shuichi Oka , Shusaku Yanagawa , Kiwamu Adachi
发明人： Shuichi Oka , Shusaku Yanagawa , Kiwamu Adachi
IPC分类号： H05K1/16 , H05K3/00 , H05K7/06
CPC分类号： H01G4/005 , H01G4/33 , H01L21/4857 , H01L23/49805 , H01L23/49822 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2924/30107 , H01L2924/3011 , H05K1/162 , H05K3/4652 , Y10T156/10 , H01L2924/00014 , H01L2924/00
摘要： A multilayer wiring board includes: a functional area which includes a thin film capacitor having a dielectric layer between an upper electrode and a lower electrode; and a peripheral area other than the functional area, wherein a mooring portion in which the dielectric layer and a conductive layer are laminated is provided in at least a portion of the peripheral area, and a roughness of a surface of the conductive layer which contacts the dielectric layer is greater than a roughness of a surface of the upper electrode or the lower electrode which contacts the dielectric layer.
摘要翻译：多层布线基板包括：功能区域，其包括在上电极和下电极之间具有介电层的薄膜电容器; 以及除了功能区域以外的周边区域，其中在周边区域的至少一部分中设置有其中层叠有电介质层和导电层的系泊部分，并且导电层的表面的粗糙度与电介质层大于与电介质层接触的上电极或下电极的表面的粗糙度。

8. 发明申请

US20110114376A1 Printed-circuit board and manufacturing method thereof 失效
标题翻译：印刷电路板及其制造方法
公开(公告)号：US20110114376A1
公开(公告)日：2011-05-19
申请号：US12923997
申请日：2010-10-20
申请人： Mitsuharu Shoji , Kiwamu Adachi
发明人： Mitsuharu Shoji , Kiwamu Adachi
IPC分类号： H05K1/16 , H05K3/10
CPC分类号： H05K1/162 , H05K2201/09509 , H05K2201/09763 , H05K2203/125
摘要： A method for manufacturing a printed-circuit board including: a capacitive element forming step of embedding a capacitive element in a substrate resin layer inside a substrate that includes a plurality of wiring layers laminated with the substrate resin layer interposed in between, the capacitive element forming step including forming a lower electrode using a conductive layer on one of the plurality of wiring layers, or using one of the plurality of wiring layers; forming a crystalline metal oxide-containing capacitor dielectric film at a temperature at or below a heat-resistant temperature of the substrate resin layer, and at or above room temperature; and forming an upper electrode on an upper surface of the capacitor dielectric film on the side opposite to the lower electrode.
摘要翻译：一种印刷电路板的制造方法，其特征在于，包括：电容元件形成步骤，将电容元件嵌入到基板内部的基板树脂层内，所述基板包括与介于其间的基板树脂层层叠的多个布线层，所述电容元件形成包括在所述多个布线层之一上使用导电层形成下电极，或者使用所述多个布线层中的一个布线层; 在等于或低于衬底树脂层的耐热温度或低于室温的温度下形成含结晶金属氧化物的电容器电介质膜; 以及在所述电容器电介质膜的与所述下电极相对的一侧的上表面上形成上电极。

9. 发明授权

US06445027B2 Method of manufacturing electronic component having capacitor element and resistor element, method of manufacturing semiconductor device, and semiconductor device 失效
标题翻译：具有电容器元件和电阻元件的电子部件的制造方法，半导体装置的制造方法以及半导体装置
公开(公告)号：US06445027B2
公开(公告)日：2002-09-03
申请号：US09766729
申请日：2001-01-22
申请人： Kiwamu Adachi
发明人： Kiwamu Adachi
IPC分类号： H01L31119
CPC分类号： H01L27/0682 , H01L21/3105 , H01L21/3143 , H01L21/31604 , H01L21/31662 , H01L21/31683 , H01L28/20 , H01L28/40
摘要： A method of manufacturing an electronic component having a capacitor element and a resistor element, in which such capacitor element and such resistor element are individually formed in the material layer (for example, a tantalum oxide film formed by the CVD process) by locally subjecting such material layer to different kinds of treatment, such as nitriding and oxidation, is provided. There is also provided a method of manufacturing a semiconductor device having a capacitor element and a resistor element, in which such capacitor element and such resistor element are individually formed in the same material layer by locally subjecting such material layer to different kinds of treatment. There is still also provided a semiconductor device having a capacitor element and a resistor element thus formed. According to the present invention, a material excellent as that for capacitor element and also suitable for other applications is used, and the material is effectively converted into other materials suitable for the capacitor element and resistor element, respectively. Thus the present invention can add value of such material, and allows a positive attitude to be taken in facility investment for such material and introduction of other similar new materials.
摘要翻译：一种制造具有电容器元件和电阻元件的电子元件的方法，其中通过将这样的电容器元件和电阻元件局部地进行这样的处理，在材料层（例如，通过CVD工艺形成的氧化钽膜）中分别形成这样的电容器元件和这种电阻元件提供材料层到不同种类的处理，如氮化和氧化。还提供了一种制造具有电容器元件和电阻元件的半导体器件的方法，其中通过对这种材料层进行不同种类的处理而将这种电容器元件和这种电阻元件分别形成在相同的材料层中。还提供了一种具有如此形成的电容器元件和电阻元件的半导体器件。根据本发明，使用与电容器元件一样优异并且也适用于其它应用的材料，并且该材料分别被有效地转换成适用于电容器元件和电阻元件的其它材料。因此，本发明可以增加这种材料的价值，并且允许对这种材料的设备投资采取积极的态度并引入其他类似的新材料。

10. 发明授权

US09672983B2 Peel resistant multilayer wiring board with thin film capacitor and manufacturing method thereof 有权
公开(公告)号：US09672983B2
公开(公告)日：2017-06-06
申请号：US13480925
申请日：2012-05-25
申请人： Shuichi Oka , Shusaku Yanagawa , Kiwamu Adachi
发明人： Shuichi Oka , Shusaku Yanagawa , Kiwamu Adachi
IPC分类号： H05K1/16 , H01G4/005 , H01G4/33 , H01L23/498 , H01L21/48 , H05K3/46
CPC分类号： H01G4/005 , H01G4/33 , H01L21/4857 , H01L23/49805 , H01L23/49822 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2924/30107 , H01L2924/3011 , H05K1/162 , H05K3/4652 , Y10T156/10 , H01L2924/00014 , H01L2924/00
摘要： A multilayer wiring board includes: a functional area which includes a thin film capacitor having a dielectric layer between an upper electrode and a lower electrode; and a peripheral area other than the functional area, wherein a mooring portion in which the dielectric layer and a conductive layer are laminated is provided in at least a portion of the peripheral area, and a roughness of a surface of the conductive layer which contacts the dielectric layer is greater than a roughness of a surface of the upper electrode or the lower electrode which contacts the dielectric layer.

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