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1. 发明授权

US5882962A Method of fabricating MOS transistor having a P.sup.+ -polysilicon gate 失效
标题翻译：制造具有P + - 多晶硅栅极的MOS晶体管的方法
公开(公告)号：US5882962A
公开(公告)日：1999-03-16
申请号：US688168
申请日：1996-07-29
申请人： Kuo-Shu Tseng , Chi-Hua Yu
发明人： Kuo-Shu Tseng , Chi-Hua Yu
IPC分类号： H01L21/28 , H01L21/8234 , H01L29/49 , H01L21/336
CPC分类号： H01L29/4925 , H01L21/28052 , H01L21/28061 , H01L21/82345 , H01L21/823468 , H01L29/4933
摘要： A method of forming a MOS transistor having a p.sup.+ -polysilicon gate includes doping an amorphous silicon layer with phosphorus, thereby forming a n.sup.- amorphous silicon layer atop of a gate oxide. The n.sup.- amorphous silicon layer is then doped with boron to convert the n.sup.- amorphous silicon layer into a p.sup.+ -amorphous silicon layer. The p.sup.+ -amorphous silicon layer is then thermally treated to convert the p.sup.+ -amorphous silicon layer into a p.sup.+ -polysilicon layer. The p.sup.+ -polysilicon layer is then patterned into a gate for a MOS transistor. The phosphorus ions in the p.sup.+ -polysilicon help to fix the boron ions in the polysilicon gate, thereby reducing the diffusion of the boron ions and penetration of boron into the gate oxide.
摘要翻译：形成具有p +多晶硅栅极的MOS晶体管的方法包括用磷掺杂非晶硅层，从而在栅极氧化物的顶部形成n-非晶硅层。然后用硼掺杂n型非晶硅层，以将n型非晶硅层转化成p + - 非晶硅层。然后对p + - 非晶硅层进行热处理以将p + - 非晶硅层转化为p + - 多晶硅层。然后将p +多晶硅层图案化成用于MOS晶体管的栅极。 p + - 多晶硅中的磷离子有助于固定多晶硅栅极中的硼离子，从而减少硼离子的扩散和硼渗透到栅极氧化物中。

2. 发明授权

US5877052A Resolution of hemispherical grained silicon peeling and row-disturb problems for dynamic random access memory, stacked capacitor structures 失效
标题翻译：用于动态随机存取存储器，堆叠电容器结构的半球形硅剥离和行干扰问题的分辨率
公开(公告)号：US5877052A
公开(公告)日：1999-03-02
申请号：US94463
申请日：1998-06-11
申请人： Dahcheng Lin , Jung-Ho Chang , Hsi-Chuan Chen , Kuo-Shu Tseng
发明人： Dahcheng Lin , Jung-Ho Chang , Hsi-Chuan Chen , Kuo-Shu Tseng
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/8234 , H01L21/20
CPC分类号： H01L27/10852 , H01L28/84
摘要： A method for creating stacked capacitor structures, with increased surface area, obtained using storage node electrode structures comprised of an HSG silicon layer, on a heavily doped amorphous silicon layer, both overlying polysilicon storage node shapes, has been developed. A dilute hydrofluoric acid pre-clean procedure is used prior to depositing a heavily doped amorphous silicon layer, on underlying polysilicon storage node shapes. An overlying second amorphous silicon layer is in situ deposited, in the same furnace used for the prior deposition of heavily doped amorphous silicon layer, followed by an in situ seeding/annealing procedure, converting the second amorphous silicon layer to an HSG silicon layer. This invention features the use of the acid pre-clean, to improve adhesion of the heavily doped amorphous silicon layer, to underlying polysilicon storage node shapes. In addition the width of the polysilicon storage node shapes is initially designed to be narrow, to accept subsequent amorphous silicon depositions, and thus to result in the desired spacing between storage node electrodes, after deposition of the amorphous silicon layers, on the sides of the polysilicon storage node shapes.
摘要翻译：已经开发了一种用于产生堆叠电容器结构的方法，该堆叠电容器结构具有增加的表面积，其使用由HSG硅层组成的存储节点电极结构，在重掺杂非晶硅层上，覆盖多晶硅存储节点形状。在沉积重掺杂的非晶硅层之前，使用稀氢氟酸预清洁程序，在下面的多晶硅存储节点形状上。在与先前沉积重掺杂的非晶硅层相同的炉中原位沉积上覆的第二非晶硅层，随后进行原位接种/退火程序，将第二非晶硅层转化为HSG硅层。本发明的特征在于使用酸预清洁剂来改善重掺杂非晶硅层对下层多晶硅储存节点形状的粘附性。此外，多晶硅存储节点形状的宽度最初被设计为窄，以接受随后的非晶硅沉积，并且因此在沉积非晶硅层之后在存储节点电极之间产生期望的间隔多晶硅储存节点形状。

3. 发明授权

US6046083A Growth enhancement of hemispherical grain silicon on a doped polysilicon storage node capacitor structure, for dynamic random access memory applications 失效
标题翻译：生长增强的半球晶硅在掺杂多晶硅存储节点电容器结构上，用于动态随机存取存储器应用
公开(公告)号：US6046083A
公开(公告)日：2000-04-04
申请号：US105185
申请日：1998-06-26
申请人： Dahcheng Lin , Jung-Ho Chang , Hsi-Chuan Chen , Kuo-Shu Tseng
发明人： Dahcheng Lin , Jung-Ho Chang , Hsi-Chuan Chen , Kuo-Shu Tseng
IPC分类号： H01L21/02 , H01L21/20 , H01L21/8242
CPC分类号： H01L28/82 , H01L28/84 , H01L28/91
摘要： A process for creating a storage node electrode for a DRAM capacitor structure, featuring increased surface area accomplished using an HSG silicon layer as the top layer for the storage node electrode, has been developed. The process features the use of a composite buffer layer of undoped and lightly doped amorphous silicon layers, located overlying a heavily doped amorphous silicon layer, and then followed by the deposition of HSG silicon seeds. A first anneal cycle then allows formation of an undoped HSG silicon layer to be realized on the underlying heavily doped amorphous silicon layer, via consumption of the HSG seeds, and of the composite buffer layer of undoped and lightly doped amorphous silicon layers. A second anneal cycle then allows dopant from the underlying heavily doped amorphous silicon layer to reach the undoped HSG silicon layer, resulting in a doped HSG silicon layer. Patterning, or CMP, of the doped HSG silicon layer, and of the heavily doped amorphous silicon layer, results in the creation of a storage node electrode. The use of the composite buffer layer allows the growth of an undoped HSG silicon layer to be achieved, thus maximizing uniformity and HSG silicon roughness, while the anneal cycle, applied to the undoped HSG silicon layer, results in the attainment of the doped HSG silicon layer, offering reduced capacitance depletion compared to undoped HSG silicon counterparts.
摘要翻译：已经开发了用于创建用于DRAM电容器结构的存储节点电极的处理，其特征在于使用HSG硅层作为存储节点电极的顶层而实现的增加的表面积。该方法的特征在于使用位于重掺杂非晶硅层上方的未掺杂和轻掺杂的非晶硅层的复合缓冲层，然后沉积HSG硅晶种。第一退火循环然后允许通过消耗HSG晶种和未掺杂和轻掺杂的非晶硅层的复合缓冲层，在下面的重掺杂非晶硅层上形成未掺杂的HSG硅层。然后第二退火循环允许来自下面的重掺杂非晶硅层的掺杂剂到达未掺杂的HSG硅层，产生掺杂的HSG硅层。掺杂HSG硅层和重掺杂非晶硅层的图案化或CMP形成存储节点电极的产生。使用复合缓冲层允许实现未掺杂的HSG硅层的生长，从而最大化均匀性和HSG硅粗糙度，而施加到未掺杂的HSG硅层的退火循环导致获得掺杂的HSG硅与未掺杂的HSG硅对应物相比，提供了减少的电容耗尽。

4. 发明授权

US5746512A Method for reducing crack of polysilicon in a quartz tube and boat 失效
标题翻译：降低石英管和船中多晶硅裂纹的方法
公开(公告)号：US5746512A
公开(公告)日：1998-05-05
申请号：US711650
申请日：1996-09-10
申请人： Liang-Gi Yao , Kuo-Shu Tseng
发明人： Liang-Gi Yao , Kuo-Shu Tseng
IPC分类号： C23C16/44 , C23C16/46 , G01N25/00
CPC分类号： C23C16/463 , C23C16/4401 , C23C16/46
摘要： The present invention relates to a method that reduces the thermal gradient at polymorphic transformation of polysilicon. The cooling rate of conventional furnaces is too rapid in currently used processes. The thermal process includes high stress from polymorphic transformation, which causes the peeling of a polysilicon film and microcracking of the quartz tube and wafer boat. The present invention suggests steps following of reducing cracks of polysilicon in a quartz tube and boat. At first, determines the temperature of polymorphic transformation of said quartz tube and boat. Next, reduces the temperature gradient during heating or cooling of said quartz tube and boat during said temperature of polysilicon transformation. Furthermore, the heating or cooling rates of the furnace is limited to the range of 0.1.degree.-2.degree. C./min to reduce the temperature gradient inside the furnace tube. Therefore, the thermal stress that is caused by the phase transition of the quartz is reduced by the invention and the particles and microcrack issues are also reduced by the invention.
摘要翻译：本发明涉及降低多晶硅多晶转化温度梯度的方法。常规炉的冷却速度在当前使用的工艺中过快。热过程包括多晶型转变的高应力，这导致多晶硅膜的剥离和石英管和晶片舟的微裂纹。本发明提出了在石英管和船中减少多晶硅裂纹的步骤。首先，确定所述石英管和船的多晶型转化温度。接下来，在所述多晶硅转化温度期间，降低所述石英管和舟皿的加热或冷却期间的温度梯度。此外，炉的加热或冷却速度限制在0.1℃-2℃/ min的范围内，以降低炉管内的温度梯度。因此，通过本发明减少了由石英的相变引起的热应力，并且本发明也减少了颗粒和微裂纹问题。

5. 发明申请

US20130026381A1 DYNAMIC, REAL TIME ULTRAVIOLET RADIATION INTENSITY MONITOR 审中-公开
标题翻译：动态，实时超紫外线强度监测
公开(公告)号：US20130026381A1
公开(公告)日：2013-01-31
申请号：US13190260
申请日：2011-07-25
申请人： Gang-Le Huang , Yeh-Chieh Wang , Jiun-Rong Pai , Hsu-Shui Liu , Kuo-Shu Tseng , Chien-Ta Lee
发明人： Gang-Le Huang , Yeh-Chieh Wang , Jiun-Rong Pai , Hsu-Shui Liu , Kuo-Shu Tseng , Chien-Ta Lee
IPC分类号： G01J3/30 , G01J5/08
CPC分类号： G01J1/429 , B05D3/067 , G01J1/0425 , G01J1/10 , G05D25/00 , H01J37/32
摘要： An apparatus and method for detecting an intensity of radiation in a process chamber, such as an ultraviolet curing process chamber, is disclosed. An exemplary apparatus includes a process chamber having a radiation source therein, wherein the radiation source is configured to emit radiation within the process chamber; a radiation sensor attached to the process chamber; and an optical fiber coupled with the radiation source and the radiation sensor, wherein the optical fiber is configured to transmit a portion of the emitted radiation to the radiation sensor, and the radiation sensor is configured to detect an intensity of the portion of the emitted radiation via the optical fiber.
摘要翻译：公开了一种用于检测处理室中的辐射强度的装置和方法，例如紫外线固化处理室。示例性设备包括其中具有辐射源的处理室，其中所述辐射源被配置为在所述处理室内发射辐射; 附接到处理室的辐射传感器; 以及与所述辐射源和所述辐射传感器耦合的光纤，其中所述光纤被配置为将所发射的辐射的一部分传输到所述辐射传感器，并且所述辐射传感器被配置为检测所述发射辐射的所述部分的强度通过光纤。

6. 发明授权

US6037219A One step in situ doped amorphous silicon layers used for selective hemispherical grain silicon formation for crown shaped capacitor applications 失效
标题翻译：用于冠状电容器应用的选择性半球形晶粒硅形成的一步原位掺杂非晶硅层
公开(公告)号：US6037219A
公开(公告)日：2000-03-14
申请号：US105104
申请日：1998-06-25
申请人： Dahcheng Lin , Jung-Ho Chang , Hsi-Chuan Chen , Kuo-Shu Tseng
发明人： Dahcheng Lin , Jung-Ho Chang , Hsi-Chuan Chen , Kuo-Shu Tseng
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/84 , H01L28/90 , Y10S438/964
摘要： A process for creating a crown shaped storage node electrode, covered with an HSG silicon layer, used to increase the surface area, and thus the capacitance of, high density, DRAM designs, has been developed. The process features creating a crown shaped storage node shape, from a composite amorphous silicon layer, wherein the composite amorphous silicon layer is comprised of a heavily doped amorphous silicon layer, used to alleviate capacitance depletion phenomena, sandwiched between undoped, or lightly doped, amorphous silicon layers, used to selectively accept the overlying HSG silicon layer. The process also features the use an HF vapor pre-clean procedure, followed by an in situ, selective deposition of HSG silicon seeds, in a conventional LPCVD chamber, prior to anneal cycle used to form the HSG silicon layer.
摘要翻译：已经开发了用于产生用于增加表面积以及因此高密度DRAM设计的电容的用HSG硅层覆盖的冠状存储节点电极的方法。该方法特征在于从复合非晶硅层形成冠形存储节点形状，其中复合非晶硅层由用于减轻电容耗尽现象的重掺杂非晶硅层组成，夹在未掺杂或轻掺杂的非晶态之间硅层，用于选择性地接受覆盖的HSG硅层。该方法还特征在于在用于形成HSG硅层的退火循环之前，使用HF蒸汽预清洁程序，随后在常规LPCVD室中进行原位选择性沉积HSG硅种子。

7. 发明授权

US4588613A Process for reducing polymer buildup 失效
标题翻译：降低聚合物积聚的方法
公开(公告)号：US4588613A
公开(公告)日：1986-05-13
申请号：US659359
申请日：1984-10-10
申请人： Shung-Chung Liau , Kuo-Shu Tseng , Yen H. Huang
发明人： Shung-Chung Liau , Kuo-Shu Tseng , Yen H. Huang
IPC分类号： C08F2/00
CPC分类号： C08F2/004
摘要： In the polymerization of vinyl chloride monomer or a mixture of vinyl monomers having vinyl chlorides as a main component, the deposition of polymer scale on the inner walls of the polymerization vessel can be effectively reduced by coating the internal surfaces of the reactor with first, a condensation polymer of a polyhydric phenol and an aldehyde and second, a crosslinking agent to increase the insolubility of the polymeric material.
摘要翻译：在氯乙烯单体或具有氯乙烯作为主要成分的乙烯基单体的混合物的聚合中，通过首先将反应器的内表面涂覆在聚合容器的内壁上，可以有效地降低聚合物垢的沉积，多元酚和醛的缩合聚合物，其次是交联剂，以增加聚合物材料的不溶性。

8. 发明申请

US20130193350A1 WAFER CURING APPARATUS HAVING IMPROVED SHRINKAGE 审中-公开
标题翻译：具有改进收缩的卷边固化装置
公开(公告)号：US20130193350A1
公开(公告)日：2013-08-01
申请号：US13363964
申请日：2012-02-01
申请人： Yu-Ying Lu , Ding-I Liu , Kuo-Shu Tseng , Yin-Bin Tseng , Tsung-Dar Lee , Wen-Hsiang Cheng
发明人： Yu-Ying Lu , Ding-I Liu , Kuo-Shu Tseng , Yin-Bin Tseng , Tsung-Dar Lee , Wen-Hsiang Cheng
IPC分类号： B01J19/12
CPC分类号： H01L21/67115
摘要： A wafer curing apparatus including a plate configured to pass ultraviolet light. The wafer curing apparatus further includes an antireflective coating on a light incident surface of the plate. The antireflective coating has an opening in a central portion thereof. A method of curing a wafer including emitting ultraviolet light from an ultraviolet light source. The method further includes transmitting the ultraviolet light through an ultraviolet transmissive plate having an antireflective coating thereon. The antireflective coating including an opening in a central portion thereof. The method further includes irradiating a wafer with the ultraviolet light transmitted through the ultraviolet transmissive plate.
摘要翻译：一种晶片固化装置，包括被配置为通过紫外光的板。晶片固化装置还包括在板的光入射表面上的抗反射涂层。抗反射涂层在其中心部分具有开口。一种固化晶片的方法，包括从紫外光源发射紫外光。该方法还包括通过其上具有抗反射涂层的紫外线透射板透射紫外光。该防反射涂层在其中心部分包括开口。该方法还包括用穿过紫外线透射板的紫外线照射晶片。

9. 发明授权

US08215890B2 Semiconductor wafer robot alignment system and method 有权
标题翻译：半导体晶圆机器人对准系统及方法
公开(公告)号：US08215890B2
公开(公告)日：2012-07-10
申请号：US12403077
申请日：2009-03-12
申请人： Kuo-Shu Tseng , Yi-Chang Sung , Chia-Chi Tsao , Chih-Che Lin
发明人： Kuo-Shu Tseng , Yi-Chang Sung , Chia-Chi Tsao , Chih-Che Lin
IPC分类号： B65G1/00 , B65G65/00
CPC分类号： H01L21/681 , H01L21/67265 , Y10S414/135 , Y10S414/136 , Y10S414/137 , Y10S414/138 , Y10S414/139 , Y10S414/14 , Y10S414/141
摘要： A method and system for aligning robotic wafer transfer systems provides a wafer cassette having one or more wafer slots having portions covered with an electrically conductive material and a sensor that is in electrical communication with the electrically conductive material. When a wafer is loaded into a wafer cassette such as may be contained within a wafer transfer module such as a FOUP, an indication of position is delivered to the sensor which detects the alignment and indicates if the loaded wafer undesirably contacts either or both of the opposed grooves that form the wafer slot of the wafer cassette. An indication of the wafer's position may be provided from the sensor to a controller that delivers a signal for aligning the wafer transfer blade of the wafer transfer robot responsive to the signal indicative of position.
摘要翻译：用于对准机器人晶片传送系统的方法和系统提供具有一个或多个晶片槽的晶片盒，所述晶片槽具有覆盖有导电材料的部分和与导电材料电连通的传感器。当将晶片装载到诸如可以包含在诸如FOUP的晶片传送模块中的晶片盒中时，将位置的指示传送到传感器，该传感器检测对准并指示加载的晶片是否不期望地接触形成晶片盒的晶片槽的相对的槽。可以从传感器向控制器提供晶片位置的指示，该控制器响应于指示位置的信号递送用于对准晶片传送机械手的晶片传送机构的信号。

10. 发明申请

US20080171647A1 LOW TEMPERATURE COFIRED CERAMIC MATERIALS 审中-公开
标题翻译：低温辅助陶瓷材料
公开(公告)号：US20080171647A1
公开(公告)日：2008-07-17
申请号：US11623926
申请日：2007-01-17
申请人： Wei-Chang Lee , Yin-Chang Wu , Kuo-Shu Tseng
发明人： Wei-Chang Lee , Yin-Chang Wu , Kuo-Shu Tseng
IPC分类号： C03C1/00
CPC分类号： C04B35/117 , C04B35/581 , C04B2235/365 , Y10T428/12528
摘要： A low temperature cofired ceramic material mainly includes that mixed evenly with high thermal conductivity ceramic materials (AlN) and Borosilicate powder glass materials.
摘要翻译：低温共烧陶瓷材料主要包括与高导热陶瓷材料（AlN）和硼硅酸盐粉末玻璃材料均匀混合。

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