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1. 发明授权

US08344775B2 Clock delay correcting device and semiconductor device having the same 有权
标题翻译：时钟延迟校正装置及其半导体装置
公开(公告)号：US08344775B2
公开(公告)日：2013-01-01
申请号：US12774602
申请日：2010-05-05
申请人： Kwang-Jin Na
发明人： Kwang-Jin Na
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , G11C7/04 , G11C7/1066 , G11C7/1084 , G11C7/1093 , G11C7/222 , G11C29/025 , G11C29/028 , G11C29/50008 , H03K2005/00052
摘要： A semiconductor device includes an on-die termination circuit, a clock input unit, a clock phase mixing unit, and a data input/output unit. The on-die termination circuit is configured to calibrate a resistance of a termination pad and output an impedance matching code. The clock input unit is configured to receive a data clock. The clock phase mixing unit is configured to receive the data clock through the clock input unit and a delayed data clock, which is generated by delaying the data clock by a predetermined time, mix a phase of the data clock and a phase of the delayed data clock at a ratio corresponding to the impedance matching code, and output a phase-mixed data clock. The data input/output unit is configured to input/output a data signal in response to the phase-mixed data clock.
摘要翻译：半导体器件包括片上终端电路，时钟输入单元，时钟相位混合单元和数据输入/输出单元。片上终端电路被配置为校准终端焊盘的电阻并输出阻抗匹配代码。时钟输入单元被配置为接收数据时钟。时钟相位混合单元被配置为通过时钟输入单元接收数据时钟，并且通过将数据时钟延迟预定时间而产生的延迟数据时钟，将数据时钟的相位和延迟数据的相位混合时钟以与阻抗匹配码相对应的比率输出，并输出相位混合数据时钟。数据输入/输出单元被配置为响应于相位混合数据时钟输入/输出数据信号。

2. 发明授权

US08222934B2 DLL circuit and method of controlling the same 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US08222934B2
公开(公告)日：2012-07-17
申请号：US13038604
申请日：2011-03-02
申请人： Kwang-Jin Na
发明人： Kwang-Jin Na
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/07 , H03L7/0812 , H03L7/0814 , H03L7/087
摘要： A DLL circuit includes a clock selection control unit configured to generate a clock selection signal on the basis of a phase difference between a reference clock and a feedback clock and, after the clock selection signal is generated, to generate an initialization signal. A delay control unit, when the initialization signal is enabled, transfers an initial voltage to be generated by dividing an external power supply voltage to a delay unit as a control voltage, and controls a delay operation of a delay reference clock to be selected on the basis of the clock selection signal.
摘要翻译： DLL电路包括：时钟选择控制单元，被配置为基于参考时钟和反馈时钟之间的相位差产生时钟选择信号，并且在产生时钟选择信号之后生成初始化信号。延迟控制单元，当初始化信号被使能时，通过将外部电源电压分配为延迟单元作为控制电压来传送要产生的初始电压，并且控制在所选择的延迟基准时钟的延迟操作时钟选择信号的基础。

3. 发明授权

US07800957B2 Data output circuit in semiconductor memory apparatus 有权
标题翻译：半导体存储装置中的数据输出电路
公开(公告)号：US07800957B2
公开(公告)日：2010-09-21
申请号：US12173724
申请日：2008-07-15
申请人： Kwang-Jin Na
发明人： Kwang-Jin Na
IPC分类号： G11C16/04
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1066
摘要： A data output circuit in a semiconductor memory apparatus includes a first data driving unit configured to generate a first driving data at a first timing, a first buffering unit configured to generate a first output data by buffering the first driving data, a second data driving unit configured to generate a second driving data at a second timing that is different from the first timing, and a second buffering unit configured to generate a second output data by buffering the second driving data.
摘要翻译：半导体存储装置中的数据输出电路包括：第一数据驱动单元，被配置为在第一定时产生第一驱动数据;第一缓冲单元，被配置为通过缓冲第一驱动数据产生第一输出数据;第二数据驱动单元被配置为在与第一定时不同的第二定时产生第二驱动数据，以及第二缓冲单元，被配置为通过缓冲第二驱动数据来生成第二输出数据。

4. 发明申请

US20110156784A1 CLOCK DELAY CORRECTING DEVICE AND SEMICONDUCTOR DEVICE HAVING THE SAME 有权
标题翻译：时钟校正器件和具有该器件的半导体器件
公开(公告)号：US20110156784A1
公开(公告)日：2011-06-30
申请号：US12774602
申请日：2010-05-05
申请人： Kwang-Jin Na
发明人： Kwang-Jin Na
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , G11C7/04 , G11C7/1066 , G11C7/1084 , G11C7/1093 , G11C7/222 , G11C29/025 , G11C29/028 , G11C29/50008 , H03K2005/00052
摘要： A semiconductor device includes an on-die termination circuit, a clock input unit, a clock phase mixing unit, and a data input/output unit. The on-die termination circuit is configured to calibrate a resistance of a termination pad and output an impedance matching code. The clock input unit is configured to receive a data clock. The clock phase mixing unit is configured to receive the data clock through the clock input unit and a delayed data clock, which is generated by delaying the data clock by a predetermined time, mix a phase of the data clock and a phase of the delayed data clock at a ratio corresponding to the impedance matching code, and output a phase-mixed data clock. The data input/output unit is configured to input/output a data signal in response to the phase-mixed data clock.
摘要翻译：半导体器件包括片上终端电路，时钟输入单元，时钟相位混合单元和数据输入/输出单元。片上终端电路被配置为校准终端焊盘的电阻并输出阻抗匹配代码。时钟输入单元被配置为接收数据时钟。时钟相位混合单元被配置为通过时钟输入单元接收数据时钟，并且通过将数据时钟延迟预定时间而产生的延迟数据时钟，将数据时钟的相位和延迟数据的相位混合时钟以与阻抗匹配码相对应的比率输出，并输出相位混合数据时钟。数据输入/输出单元被配置为响应于相位混合数据时钟输入/输出数据信号。

5. 发明授权

US07778095B2 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07778095B2
公开(公告)日：2010-08-17
申请号：US12000698
申请日：2007-12-17
申请人： Kwang-Jin Na
发明人： Kwang-Jin Na
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , H03L7/0814
摘要： A semiconductor memory device includes a delay locked loop (DLL) unit configured to generate a plurality of DLL clocks, each having a different phase according to delay values predefined by a DLL operation; a data output buffering unit configured to output data in response to the DLL clocks; and a skew compensating unit disposed between the DLL unit and the data output buffering unit to remove a clock skew occurring when the DLL clocks are transferred to the data output buffering unit.
摘要翻译：半导体存储器件包括延迟锁定环（DLL）单元，被配置为产生多个DLL时钟，每个DLL时钟根据由DLL操作预定义的延迟值具有不同的相位; 数据输出缓冲单元，被配置为响应于所述DLL时钟输出数据; 以及偏置补偿单元，设置在DLL单元和数据输出缓冲单元之间，以消除当DLL时钟被传送到数据输出缓冲单元时发生的时钟偏移。

6. 发明授权

US08258843B2 Semiconductor device and method for operating the same 有权
标题翻译：半导体装置及其操作方法
公开(公告)号：US08258843B2
公开(公告)日：2012-09-04
申请号：US12645970
申请日：2009-12-23
申请人： Hoon Choi , Kwang-Jin Na
发明人： Hoon Choi , Kwang-Jin Na
IPC分类号： H03K3/16 , H03K3/30
CPC分类号： G11C11/4076 , G11C7/1072 , G11C7/222
摘要： A semiconductor device includes a clock delay section configured to receive an external clock signal, reflect different delay amounts on the external clock signal, and generate a plurality of synchronization clock signals, a clock synchronization section configured to synchronize a clock enable signal with each of the plurality of synchronization clock signals in an order beginning with a synchronization clock signal, on which a largest delay amount is reflected, to a synchronization clock signal, on which a smallest delay amount is reflected, and to generate a synchronized clock enable signal, and an internal clock generation section configured to generate an internal clock signal corresponding to the external clock signal, and to be on/off controlled in its operation in response to the synchronized clock enable signal.
摘要翻译：半导体器件包括：时钟延迟部，被配置为接收外部时钟信号，反映外部时钟信号的不同延迟量，并产生多个同步时钟信号;时钟同步部，被配置为使时钟使能信号与多个同步时钟信号以从反射最大延迟量的同步时钟信号开始，反射到最小延迟量的同步时钟信号，并产生同步时钟使能信号，并且内部时钟生成部，被配置为生成与外部时钟信号对应的内部时钟信号，并且响应于同步的时钟使能信号而在其操作中进行开/关控制。

7. 发明申请

US20090115486A1 Apparatus and method for generating multi-phase clocks 有权
标题翻译：用于产生多相时钟的装置和方法
公开(公告)号：US20090115486A1
公开(公告)日：2009-05-07
申请号：US12003681
申请日：2007-12-31
申请人： Kwang-Jin Na
发明人： Kwang-Jin Na
IPC分类号： G06F1/04
CPC分类号： G06F1/06 , H03K5/1504 , H03K2005/00026 , H03L7/0812 , H03L7/095
摘要： An apparatus for generating multi-phase clocks in accordance with the present invention includes a clock delay configured to delay a source clock by a delay time corresponding to a control signal to generate a plurality of clocks; a clock multiplexer configured to output a first clock for a first locking region and a second clock for a second locking region sequentially as a selected clock in response to a locking detection signal; a phase detector configured to detect a phase of the selected clock in comparison to a phase of the source clock to output a phase detection signal; and a control voltage signal generator configured to generate the control signal corresponding to the phase detection signal.
摘要翻译：根据本发明的用于产生多相时钟的装置包括时钟延迟，其被配置为将源时钟延迟与控制信号相对应的延迟时间以产生多个时钟; 时钟多路复用器，被配置为响应于锁定检测信号，顺序地输出用于第一锁定区域的第一时钟和第二锁定区域的第二时钟作为选择的时钟; 相位检测器，被配置为与源时钟的相位相比检测所选择的时钟的相位，以输出相位检测信号; 以及控制电压信号发生器，被配置为产生对应于相位检测信号的控制信号。

8. 发明授权

US07317337B2 Output driver in semiconductor device 有权
标题翻译：半导体器件中的输出驱动器
公开(公告)号：US07317337B2
公开(公告)日：2008-01-08
申请号：US11323584
申请日：2005-12-29
申请人： Kwang-Jin Na
发明人： Kwang-Jin Na
IPC分类号： H03K19/0175
CPC分类号： H03K19/00384
摘要： There is provided an output driver of a semiconductor device in which a slew rate variance is small despite an environmental change and a slew rate can be easily controlled. The output driver includes a main driver for driving an output terminal, a delay unit for controlling a delay time of a driving control signal in response to a delay control signal, and a pre-driver for pre-driving an input terminal of the main driver in response to an output signal of the delay unit.
摘要翻译：提供尽管环境变化并且转换速率可以容易地控制的转换速率变化小的半导体器件的输出驱动器。输出驱动器包括用于驱动输出端子的主驱动器，用于响应于延迟控制信号来控制驱动控制信号的延迟时间的延迟单元，以及用于预驱动主驱动器的输入端子的预驱动器响应延迟单元的输出信号。

9. 发明授权

US06982924B2 Data output control circuit 有权
标题翻译：数据输出控制电路
公开(公告)号：US06982924B2
公开(公告)日：2006-01-03
申请号：US10875387
申请日：2004-06-25
申请人： Kwang-Jin Na
发明人： Kwang-Jin Na
IPC分类号： G11C8/00
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C7/222
摘要： A data output control circuit for use in a synchronous semiconductor memory device including: a first data output enable signal generation unit for receiving an internal signal and generating a rising data output enable signal synchronizing with a rising edge of a DLL clock signal according to a CAS latency; and a second data output enable signal generation unit for receiving the rising data output enable signal and generating a falling data output enable signal synchronizing with a falling edge of the DLL clock signal.
摘要翻译：一种用于同步半导体存储器件的数据输出控制电路，包括：第一数据输出使能信号产生单元，用于接收内部信号，并产生与根据CAS的DLL时钟信号的上升沿同步的上升数据输出使能信号潜伏; 以及第二数据输出使能信号生成单元，用于接收上升数据输出使能信号，并产生与DLL时钟信号的下降沿同步的下降数据输出使能信号。

10. 发明授权

US08514639B2 Semiconductor memory device and method for operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08514639B2
公开(公告)日：2013-08-20
申请号：US12982648
申请日：2010-12-30
申请人： Kwang-Jin Na
发明人： Kwang-Jin Na
IPC分类号： G11C7/00
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/1093 , G11C16/32
摘要： A semiconductor memory device includes a plurality of banks, a clock input unit configured to receive an external data clock, an internal data clock generation unit configured to receive the external data clock from the clock input unit and generate an internal data clock by delaying the external data clock by a delay amount which changes in correspondence to the number of banks activated among the plurality of banks, and a data buffer unit configured to buffer a data signal in response to the internal data clock.
摘要翻译：半导体存储器件包括多个存储体，被配置为接收外部数据时钟的时钟输入单元，配置为从时钟输入单元接收外部数据时钟并通过延迟外部数据时钟产生内部数据时钟的内部数据时钟生成单元数据时钟延迟量，其对应于在多个存储体中激活的存储体的数量而改变;以及数据缓冲器单元，被配置为响应于内部数据时钟缓冲数据信号。

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