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1. 发明申请

US20100217905A1 Synchronization Optimized Queuing System 失效
标题翻译：同步优化排队系统
公开(公告)号：US20100217905A1
公开(公告)日：2010-08-26
申请号：US12391373
申请日：2009-02-24
申请人： Lakshminarayana Arimilli , Claude Basso , Piyush Chaudhary , Benard C. Drerup , Jody B. Joyner , Jan-Bernd Themann , Christoph Raisch , Colin B. Verrilli
发明人： Lakshminarayana Arimilli , Claude Basso , Piyush Chaudhary , Benard C. Drerup , Jody B. Joyner , Jan-Bernd Themann , Christoph Raisch , Colin B. Verrilli
IPC分类号： G06F13/24 , G06F9/54
CPC分类号： G06F9/545 , G06F9/546
摘要： A synchronization optimized queuing method and device to minimize software/hardware interaction in network interface hardware during an end-of-initiative process, including network adapter queue implementations for network interface hardware for optimized communication in a computer system. An end-of-initiative procedure to ensure that the network interface hardware has received an interrupt enable and to recheck the interrupt queue is unnecessary in the present invention.
摘要翻译：一种同步优化的排队方法和设备，用于最大程度地减少网络接口硬件中的软件/硬件交互，包括用于计算机系统中优化通信的网络接口硬件的网络适配器队列实现。在本发明中，确保网络接口硬件已经接收到中断使能并重新检查中断队列的最终主动性过程是不必要的。

2. 发明授权

US08302109B2 Synchronization optimized queuing system 失效
标题翻译：同步优化排队系统
公开(公告)号：US08302109B2
公开(公告)日：2012-10-30
申请号：US12391373
申请日：2009-02-24
申请人： Lakshminarayana Arimilli , Claude Basso , Piyush Chaudhary , Bernard C. Drerup , Jody B. Joyner , Jan-Bernd Themann , Christoph Raisch , Colin B. Verrilli
发明人： Lakshminarayana Arimilli , Claude Basso , Piyush Chaudhary , Bernard C. Drerup , Jody B. Joyner , Jan-Bernd Themann , Christoph Raisch , Colin B. Verrilli
IPC分类号： G06F3/03
CPC分类号： G06F9/545 , G06F9/546
摘要： A synchronization optimized queuing method and device to minimize software/hardware interaction in network interface hardware during an end-of-initiative process, including network adapter queue implementations for network interface hardware for optimized communication in a computer system. An end-of-initiative procedure to ensure that the network interface hardware has received an interrupt enable and to recheck the interrupt queue is unnecessary in the present invention.
摘要翻译：一种同步优化的排队方法和设备，用于最大程度地减少网络接口硬件中的软件/硬件交互，包括用于计算机系统中优化通信的网络接口硬件的网络适配器队列实现。在本发明中，确保网络接口硬件已经接收到中断使能并重新检查中断队列的最终主动性过程是不必要的。

3. 发明授权

US07921316B2 Cluster-wide system clock in a multi-tiered full-graph interconnect architecture 有权
标题翻译：多层全图互连架构中的群集范围的系统时钟
公开(公告)号：US07921316B2
公开(公告)日：2011-04-05
申请号：US11853522
申请日：2007-09-11
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G06F1/00 , G06F1/04 , G06F1/12
CPC分类号： G06F1/10 , G06F1/12
摘要： Mechanisms for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.
摘要翻译：提供了一种在多层全图（MTFG）互连架构中提供集群范围的系统时钟的机制。计算群集中的每个处理器芯片发送的心跳信号同步。基于同步的心跳信号，在每个处理器芯片中产生内部系统时钟信号。结果，每个处理器芯片的内部系统时钟信号被同步，因为作为内部系统时钟信号的基础的心跳信号被同步。提供了用于使用同一处理器书中的处理器芯片的直接耦合，同一超级节点中的不同处理器书以及MTFG互连体系结构的不同超节点中的不同处理器簿来执行这种同步的机制。

4. 发明申请

US20100262787A1 TECHNIQUES FOR CACHE INJECTION IN A PROCESSOR SYSTEM BASED ON A SHARED STATE 有权
标题翻译：基于共享状态的处理器系统中缓存注入的技术
公开(公告)号：US20100262787A1
公开(公告)日：2010-10-14
申请号：US12421338
申请日：2009-04-09
申请人： Lakshminarayana Baba Arimilli , Ravi K. Arimilli , Jody B. Joyner , William J. Starke
发明人： Lakshminarayana Baba Arimilli , Ravi K. Arimilli , Jody B. Joyner , William J. Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/1027 , G06F12/123
摘要： A technique for performing cache injection includes monitoring, at a host fabric interface, snoop responses to an address on a bus. When the snoop responses indicate a data block associated with the address is in a shared state, input/output data associated with the address on the bus is directed to a cache that includes the data block in the shared state and is located physically closer to the host fabric interface than one or more other caches that include the data block associated with the address in the shared state.
摘要翻译：用于执行高速缓存注入的技术包括在主机结构接口处监视对总线上的地址的响应。当窥探响应指示与地址相关联的数据块处于共享状态时，与总线上的地址相关联的输入/输出数据被引导到包括处于共享状态的数据块的高速缓存，并且物理上更靠近主机结构接口比包括与共享状态中的地址相关联的数据块的一个或多个其他高速缓存。

5. 发明授权

US06546469B2 Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers 失效
公开(公告)号：US06546469B2
公开(公告)日：2003-04-08
申请号：US09749328
申请日：2001-03-12
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Guy Lynn Guthrie , Jody B. Joyner
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Guy Lynn Guthrie , Jody B. Joyner
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor computer system in which snoop operations of the caches are synchronized to allow the issuance of a cache operation during a cycle which is selected based on the particular manner in which the caches have been synchronized. Each cache controller is aware of when these synchronized snoop tenures occur, and can target these cycles for certain types of requests that are sensitive to snooper retries, such as kill-type operations. The synchronization may set up a priority scheme for systems with multiple interconnect buses, or may synchronize the refresh cycles of the DRAM memory of the snooper's directory. In another aspect of the invention, windows are created during which a directory will not receive write operations (i.e., the directory is reserved for only read-type operations). The invention may be implemented in a cache hierarchy which provides memory arranged in banks, the banks being similarly synchronized. The invention is not limited to any particular type of instruction, and the synchronization functionality may be hardware or software programmable.

6. 发明授权

US06477613B1 Cache index based system address bus 有权
标题翻译：基于缓存索引的系统地址总线
公开(公告)号：US06477613B1
公开(公告)日：2002-11-05
申请号：US09345302
申请日：1999-06-30
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0811 , G06F12/0895 , G06F12/0897
摘要： Following a cache miss by an operation, the address for the operation is transmitted on the bus coupling the cache to lower levels of the storage hierarchy. A portion of the address including the index field is transmitted during a first bus cycle, and may be employed to begin directory lookups in lower level storage devices before the address tag is received. The remainder of the address is transmitted during subsequent bus cycles, which should be in time for address tag comparisons with the congruence class elements. To allow multiple directory lookups to be occurring concurrently in a pipelined directory, a portion of multiple addresses for several data access operations, each portion including the index field for the respective address, may be transmitted during the first bus cycle or staged in consecutive bus cycles, with the remainders of each address—including the cache tags—transmitted during the subsequent bus cycles. This allows directory lookups utilizing the index fields to be processed concurrently within a lower level storage device for multiple operations, with the address tags being provided later, but still timely for tag comparisons at the end of the directory lookup. Where the lower level storage device operates at a higher frequency than the bus, overall latency is reduced and directory bandwidth is more efficiently utilized.
摘要翻译：在操作的高速缓存未命中之后，操作的地址在将高速缓存耦合到存储层级的较低级别的总线上传输。包括索引字段的地址的一部分在第一总线周期期间被发送，并且可以用于在接收到地址标签之前开始下级存储设备中的目录查找。在随后的总线周期期间传送地址的其余部分，这些时间应与地址标签与同余类元素进行比较。为了允许在流水线目录中同时发生多个目录查找，可以在第一个总线周期期间发送多个数据访问操作的多个地址的一部分，每个部分包括相应地址的索引字段，或者在连续的总线周期中分段，每个地址的剩余部分，包括在后续总线周期期间发送的缓存标签。这允许使用索引字段的目录查找在较低级存储设备中同时处理以用于多个操作，其中地址标签稍后提供，但是在目录查找结束时仍然适合于标签比较。在较低级存储设备以比总线更高的频率工作的地方，总体延迟降低，目录带宽更有效地利用。

7. 发明授权

US06343344B1 System bus directory snooping mechanism for read/castout (RCO) address transaction 失效
标题翻译：系统总线事务与缓存标签的受害者地址
公开(公告)号：US06343344B1
公开(公告)日：2002-01-29
申请号：US09368221
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1208
CPC分类号： G06F12/0804 , G06F12/0859
摘要： In response to receiving a combined address for related data access and cast out operations, including an index identifying a congruence class containing both the target of the data access and the victim of the cast out, a single directory access is performed utilizing the index to locate the congruence class. Address tags within the congruence class are then compared to the address tag for the data access operation and the address tag for the cast out operation concurrently, generating separate hit signals as appropriate. Only a single directory access is required, however, rather than two separate directory accesses as required in the known art, taking advantage of the fact that both the data access target and the cast out victim belong to a single congruence class. Response latency is also improved, as is address bus bandwidth utilization.
摘要翻译：响应于接收到用于相关数据访问和丢弃操作的组合地址，包括标识包含数据访问目标和丢弃的受害者的同余类的索引，使用索引来定位单个目录访问一致类。然后将同余类中的地址标签与用于数据访问操作的地址标签和用于外推操作的地址标签同时进行比较，并酌情生成单独的命中信号。然而，仅需要单个目录访问，而不是如已知技术中所需的两个单独的目录访问，利用数据访问目标和丢弃的受害者都属于单个同余类的事实。响应延迟也得到改善，地址总线带宽利用率也得到提高。

8. 发明授权

US06324617B1 Method and system for communicating tags of data access target and castout victim in a single data transfer 失效
标题翻译：用于在单个数据传输中传送数据访问目标和丢弃受害者的标签的方法和系统
公开(公告)号：US06324617B1
公开(公告)日：2001-11-27
申请号：US09368222
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0804 , G06F12/0859
摘要： A combined address bus transaction contains the address tag for a data access operation target, the address tag for a victim to be replaced, and the address index field identifying the congruence class including both the target and the victim. Directory state information such as coherency state and/or LRU position for the cast out victim may also be appended to the index field and target and victim address tags within the bus operation. Address bus bandwidth utilization is thereby improved, eliminating duplicate transmission of the index field employed by separate data access and cast out operations in accordance with the existing practice. The victim may be prospectively selected concurrently with the determination of whether the target may be found within the storage device forming the combined address, improving overall performance for that device.
摘要翻译：组合的地址总线事务包含用于数据访问操作目标的地址标签，要替换的受害者的地址标签，以及标识包括目标和受害者的一致类的地址索引字段。目的地状态信息，例如用于投放受害者的一致性状态和/或LRU位置也可以附加到总线操作中的索引字段和目标和受害者地址标签。从而改善了地址总线带宽利用率，消除了根据现有实践分离数据访问和丢弃操作所采用的索引字段的重复传输。可以同时确定受害者是否可以在形成组合地址的存储设备内找到目标，从而提高该设备的整体性能。

9. 发明授权

US08417778B2 Collective acceleration unit tree flow control and retransmit 失效
标题翻译：集体加速单位树流控制和重传
公开(公告)号：US08417778B2
公开(公告)日：2013-04-09
申请号：US12640208
申请日：2009-12-17
申请人： Lakshminarayana B. Arimilli , Bernard C. Drerup , Jody B. Joyner , Paul F. Lecocq , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Bernard C. Drerup , Jody B. Joyner , Paul F. Lecocq , Hanhong Xue
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： A mechanism is provided for collective acceleration unit tree flow control forms a logical tree (sub-network) among those processors and transfers “collective” packets on this tree. The system supports many collective trees, and each collective acceleration unit (CAU) includes resources to support a subset of the trees. Each CAU has limited buffer space, and the connection between two CAUs is not completely reliable. Therefore, to address the challenge of collective packets traversing on the tree without colliding with each other for buffer space and guaranteeing the end-to-end packet delivery, each CAU in the system effectively flow controls the packets, detects packet loss, and retransmits lost packets.
摘要翻译：提供了一种用于集体加速单元树流控制的机制，形成这些处理器之间的逻辑树（子网），并在该树上传送集合分组。系统支持许多集体树，每个集体加速单元（CAU）包括支持一部分树的资源。每个CAU具有有限的缓冲区空间，两个CAU之间的连接不是完全可靠的。因此，为了解决在树上遍历的集合分组的挑战，不会相互冲突，保证端到端的分组传递，系统中的每个CAU都有效地流量控制分组，检测分组丢失，重传丢失数据包

10. 发明申请

US20090198958A1 System and Method for Performing Dynamic Request Routing Based on Broadcast Source Request Information 有权
标题翻译：基于广播源请求信息执行动态请求路由的系统和方法
公开(公告)号：US20090198958A1
公开(公告)日：2009-08-06
申请号：US12024553
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G06F13/14 , G06F9/02
CPC分类号： H04L45/122 , H04L45/06
摘要： A system and method for performing dynamic request routing based on broadcast source request information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide source request information to each of the other processor chips in the system. The source request information identifies the number of active source requests sent by the processor chip that originated the heartbeat signal. The source request information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.
摘要翻译：提供了一种基于广播源请求信息进行动态请求路由的系统和方法。系统中的每个处理器芯片可以使用其产生的同步心跳信号来向系统中的每个其他处理器芯片提供源请求信息。源请求信息标识由发起心跳信号的处理器芯片发送的活动源请求的数量。来自系统中的每个处理器芯片的源请求信息可被处理器芯片用于确定用于从源处理器芯片到目的地处理器芯片的数据的最佳路由路径。结果，当选择哪个处理器芯片来转发数据时，可以考虑在每个可能的路由路径处的每个处理器芯片处理数据的拥塞。

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