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1. 再颁专利

USRE48570E1 Memory circuit having non-volatile memory cell and methods of using 有权
公开(公告)号：USRE48570E1
公开(公告)日：2021-05-25
申请号：US16267278
申请日：2019-02-04
申请人： Lattice Semiconductor Corporation
发明人： Ronald L. Cline , Stewart G. Logie
IPC分类号： G11C7/16 , G11C17/18 , G11C17/16
摘要： One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.

2. 发明申请

US20200043553A1 MEMORY CIRCUIT HAVING NON-VOLATILE MEMORY CELL AND METHODS OF USING 审中-公开
公开(公告)号：US20200043553A1
公开(公告)日：2020-02-06
申请号：US16056390
申请日：2018-08-06
申请人： Lattice Semiconductor Corporation
发明人： Ronald L. Cline
IPC分类号： G11C14/00 , H03K19/177
摘要： One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first magnetic tunnel junction (MTJ) device, a first select device connected in series with the first MTJ device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell.

3. 发明申请

US20190279100A1 LOW LATENCY INTERRUPT ALERTS FOR ARTIFICIAL NEURAL NETWORK SYSTEMS AND METHODS 审中-公开
公开(公告)号：US20190279100A1
公开(公告)日：2019-09-12
申请号：US16290811
申请日：2019-03-01
申请人： Lattice Semiconductor Corporation
发明人： Ronald L. Cline
IPC分类号： G06N5/04 , G06K9/62 , G06N3/08 , G06F9/38
摘要： Various techniques are provided for providing neural networks with increased efficiency. In one example, a system includes a first artificial neural network (ANN), a second ANN, and a logic device. The first ANN is configured to receive a first plurality of data inputs associated with a data stream and process the first data inputs to generate a first inference output after a first latency. The second ANN is configured to receive a second plurality of data inputs associated with the data stream and process the second data inputs to generate a second inference output after a second latency less than the first latency. The logic device is configured to receive the second inference output before the first inference output is generated. Additional systems and methods are also provided.

4. 发明授权

US10559357B1 Memory circuit having non-volatile memory cell and methods of using 有权
公开(公告)号：US10559357B1
公开(公告)日：2020-02-11
申请号：US16056390
申请日：2018-08-06
申请人： Lattice Semiconductor Corporation
发明人： Ronald L. Cline
IPC分类号： G11C11/00 , G11C14/00 , H03K19/1776 , G11C11/16
摘要： One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first magnetic tunnel junction (MTJ) device, a first select device connected in series with the first MTJ device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell.

5. 发明授权

US10079054B1 Selective power gating of routing resource configuration memory bits for programmable logic devices 有权
公开(公告)号：US10079054B1
公开(公告)日：2018-09-18
申请号：US15614419
申请日：2017-06-05
申请人： Lattice Semiconductor Corporation
发明人： Senani Gunaratna , Brad Sharpe-Geisler , Ting Yew , Ronald L. Cline
IPC分类号： H03K19/177 , H01L25/00 , G11C11/413 , G11C8/14
CPC分类号： G11C11/413 , G11C5/14 , G11C8/14 , G11C11/412 , H03K19/177 , H03K19/17736 , H03K19/17744
摘要： Various techniques are provided to efficiently implement selective power gating of routing resource configuration memory bits for programmable logic devices (PLDs). In one example, a PLD includes a routing circuit configured to selectively route input nodes to an output node. The PLD further includes configuration memory cells configured to store configuration bit values to control the routing circuit. The PLD further includes a power circuit configured to power the configuration memory cells while storing the configuration bit values. The PLD further includes an enable bit memory cell configured to store an enable bit value to interrupt at least one connection of the power circuit to the configuration memory cells. The configuration memory cells are configured to provide, in response to an interruption of the connection, default configuration bit values to the routing circuit to prevent routing the input nodes to the output node. Additional systems and related methods are provided.

6. 发明申请

US20160111168A1 MEMORY CIRCUIT HAVING NON-VOLATILE MEMORY CELL AND METHODS OF USING 有权
标题翻译：具有非易失性存储单元的存储器电路及其使用方法
公开(公告)号：US20160111168A1
公开(公告)日：2016-04-21
申请号：US14887174
申请日：2015-10-19
申请人： Lattice Semiconductor Corporation
发明人： Ronald L. Cline , Stewart Logie
IPC分类号： G11C17/18 , G11C11/412 , G11C17/16
CPC分类号： G11C17/18 , G11C17/16
摘要： One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.
摘要翻译：一个方面涉及具有可编程非易失性存储器（NVM）单元的存储器电路，其被配置为产生指示NVM单元的编程状态的NVM输出信号，并且基于NVM单元的编程状态来配置易失性输出。 NVM单元包括第一反熔丝器件，在第一节点处与第一反熔丝器件串联连接的第一选择器件和第一通路器件。存储器电路还可以具有可编程（独立于NVM单元）易失性存储器（VM）单元，其被配置为在VM输入节点处接收NVM输出信号，并且生成指示VM单元的程序状态的VM输出信号。 NVM单元可以具有可单独编程的两个NV元件，并且可以通过单独的存取晶体管单独选择以驱动VM输入节点。

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