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1. 发明授权

US10417078B2 Deterministic read back and error detection for programmable logic devices 有权
公开(公告)号：US10417078B2
公开(公告)日：2019-09-17
申请号：US15482654
申请日：2017-04-07
申请人： Lattice Semiconductor Corporation
发明人： Loren McLaury , Brad Sharpe-Geisler
IPC分类号： G06F11/00 , G06F11/07 , G11C11/419 , H03K19/177 , G11C29/52
摘要： Various techniques are provided to efficiently implement deterministic read back and error detection for programmable logic devices (PLDs). In one example, a PLD includes an array of memory cells arranged in rows and columns, where at least one row includes an enable bit. The PLD further includes an address logic circuit configured to selectively assert the columns of the array by respective address lines. The PLD further includes a register configured to store a value of the enable bit in response to an assertion of an address line corresponding to the enable bit. The PLD further includes a read back circuit configured to selectively provide, for each memory cell, a data bit value stored by the memory cell or a predetermined data bit value based at least on the stored value of the register. Additional systems and related methods are provided.

2. 发明申请

US20190158073A1 MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES 审中-公开
公开(公告)号：US20190158073A1
公开(公告)日：2019-05-23
申请号：US16195762
申请日：2018-11-19
申请人： Lattice Semiconductor Corporation
发明人： Brad Sharpe-Geisler , Senani Gunaratna , Ting Yew
IPC分类号： H03K3/3562 , H03K3/356 , H03K19/177 , H03K19/00 , G06F17/50 , H03K19/173
摘要： Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.

3. 发明授权

US10141917B2 Multiple mode device implementation for programmable logic devices 有权
公开(公告)号：US10141917B2
公开(公告)日：2018-11-27
申请号：US15658356
申请日：2017-07-24
申请人： Lattice Semiconductor Corporation
发明人： Brad Sharpe-Geisler , Senani Gunaratna , Ting Yew
IPC分类号： H03K19/173 , H03K3/3562 , G06F17/50 , H03K19/177 , H03K3/356 , H03K19/00
摘要： Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.

4. 发明授权

US10079054B1 Selective power gating of routing resource configuration memory bits for programmable logic devices 有权
公开(公告)号：US10079054B1
公开(公告)日：2018-09-18
申请号：US15614419
申请日：2017-06-05
申请人： Lattice Semiconductor Corporation
发明人： Senani Gunaratna , Brad Sharpe-Geisler , Ting Yew , Ronald L. Cline
IPC分类号： H03K19/177 , H01L25/00 , G11C11/413 , G11C8/14
CPC分类号： G11C11/413 , G11C5/14 , G11C8/14 , G11C11/412 , H03K19/177 , H03K19/17736 , H03K19/17744
摘要： Various techniques are provided to efficiently implement selective power gating of routing resource configuration memory bits for programmable logic devices (PLDs). In one example, a PLD includes a routing circuit configured to selectively route input nodes to an output node. The PLD further includes configuration memory cells configured to store configuration bit values to control the routing circuit. The PLD further includes a power circuit configured to power the configuration memory cells while storing the configuration bit values. The PLD further includes an enable bit memory cell configured to store an enable bit value to interrupt at least one connection of the power circuit to the configuration memory cells. The configuration memory cells are configured to provide, in response to an interruption of the connection, default configuration bit values to the routing circuit to prevent routing the input nodes to the output node. Additional systems and related methods are provided.

5. 发明授权

US11206025B2 Input/output bus protection systems and methods for programmable logic devices 有权
公开(公告)号：US11206025B2
公开(公告)日：2021-12-21
申请号：US17332943
申请日：2021-05-27
申请人： Lattice Semiconductor Corporation
发明人： Chwei-Po Chew , Brad Sharpe-Geisler
IPC分类号： G06F13/20 , H03K19/17764 , G06F1/3234 , G05B19/05 , H03K19/17736
摘要： Systems and methods for providing external bus protection for programmable logic devices (PLDs) are disclosed. An example system includes a programmable I/O bus configured to interface with a user device over an external bus interface coupled to a PLD; a bus protection circuit arrangement integrated with the programmable I/O interface and configured to provide I/O bus supply voltage protection for the programmable I/O interface; and a bus protection control signal generator. The bus protection control signal generator generates a default bus protection control signal for the bus protection circuit arrangement of the PLD prior to completion of a power ramp performed by the user device; an intermediate bus protection control signal for the PLD prior to completion of loading a PLD configuration into a PLD fabric of the PLD; and an operational bus protection control signal for the PLD.

6. 发明申请

US20170324400A1 FLEXIBLE RIPPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES 审中-公开
公开(公告)号：US20170324400A1
公开(公告)日：2017-11-09
申请号：US15658349
申请日：2017-07-24
申请人： Lattice Semiconductor Corporation
发明人： Brad Sharpe-Geisler , Senani Gunaratna , Ting Yew
IPC分类号： H03K3/3562 , H03K19/173 , H03K19/00 , H03K3/356 , G06F17/50 , H03K19/177
CPC分类号： H03K3/35625 , G06F17/505 , G06F17/5054 , H03K3/356156 , H03K19/0016 , H03K19/173 , H03K19/17728
摘要： Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.

7. 发明授权

US09716491B2 Multiple mode device implementation for programmable logic devices 有权
公开(公告)号：US09716491B2
公开(公告)日：2017-07-25
申请号：US14610127
申请日：2015-01-30
申请人： Lattice Semiconductor Corporation
发明人： Brad Sharpe-Geisler , Senani Gunaratna , Ting Yew
IPC分类号： H03K19/177 , H03K3/3562 , H03K19/00 , H03K19/173 , G06F17/50 , H03K3/356
CPC分类号： H03K3/35625 , G06F17/505 , G06F17/5054 , H03K3/356156 , H03K19/0016 , H03K19/173 , H03K19/17728
摘要： Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.

8. 发明授权

US09515643B2 Hot-socket circuitry 有权
标题翻译：热插座电路
公开(公告)号：US09515643B2
公开(公告)日：2016-12-06
申请号：US14147796
申请日：2014-01-06
申请人： Lattice Semiconductor Corporation
发明人： Keith Truong , Brad Sharpe-Geisler , Ravi Lall , Giap Tran
IPC分类号： H03K17/08 , H03K17/687 , H02H9/04
CPC分类号： H03K17/08 , H02H9/043 , H02H9/044 , H03K17/6872
摘要： In one embodiment, an integrated circuit has hot-socket circuitry to protect I/O drivers during hot-socket events. The hot-socket circuitry has (i) N-well-to-pad switcher circuitry that ties driver PMOS N-wells to pads when the pad voltages are greater than the power-supply voltage and (ii) N-well-to-power-supply switcher circuitry that ties the driver PMOS N-wells to the power supply when the pad voltages are less than the power-supply voltage. The hot-socket circuitry also has a special PMOS device connected between the pad and a gate of at least one other PMOS device in the N-well-to-power-supply switcher circuitry to turn off the N-well-to-power-supply switcher circuitry quickly whenever the pad voltage is greater than the power-supply voltage. Applying a reduced power-supply voltage level to the gate of the special PMOS device enables the hot-socket circuitry to be implemented without having to use low Vt devices and without having to implement substantially large drive strengths.
摘要翻译：在一个实施例中，集成电路具有用于在热插座事件期间保护I / O驱动器的热插座电路。热插座电路具有：（i）当焊盘电压大于电源电压时，N-well-to-pad切换器电路将驱动器PMOS N阱连接到焊盘，以及（ii）N-well-to-power - 当焊盘电压小于电源电压时，将驱动器PMOS N阱连接到电源的供电开关电路。热插座电路还具有连接在焊盘和N阱到电源切换器电路中的至少一个其它PMOS器件的栅极之间的特殊PMOS器件，以将N阱到功率 - 每当焊盘电压大于电源电压时，电源开关电路快速。对特殊PMOS器件的栅极施加降低的电源电压使得能够实现热插座电路，而不必使用低Vt器件，而不必实现基本上大的驱动器强度。

9. 发明授权

US08643168B1 Integrated circuit package with input capacitance compensation 有权
标题翻译：具有输入电容补偿的集成电路封装
公开(公告)号：US08643168B1
公开(公告)日：2014-02-04
申请号：US13685385
申请日：2012-11-26
申请人： Lattice Semiconductor Corporation
发明人： Ban P. Wong , Brad Sharpe-Geisler
IPC分类号： H01L23/12
CPC分类号： H03K19/17712 , G01R31/318597 , G11C11/413 , G11C16/24 , G11C17/16 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/50 , H01L23/60 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/13091 , H01L2924/15311 , H03K19/177 , H03K19/17704 , H03K19/17716 , H03M1/001 , H03M1/34 , H04L25/0262 , H04L41/0806 , H04L47/10 , H01L2924/00012 , H01L2924/00
摘要： A ball-grid-array (BGA) package is disclosed that includes traces within a BGA substrate. At least one of the traces is configured to match a low-impedance load presented by a BGA substrate pad and associated circuitry on a flip-chip die to an impedance of a circuit board trace. Each configured trace includes a relatively narrow section coupling to a tapered section that widens from the relatively narrow section to join a relatively wider trace section.
摘要翻译：公开了一种包括BGA衬底内的迹线的球栅阵列（BGA）封装。至少一个迹线被配置为将由BGA衬底焊盘提供的低阻抗负载和倒装芯片上的相关电路匹配到电路板迹线的阻抗。每个配置的迹线包括耦合到锥形部分的相对窄的部分，其从相对较窄的部分变宽以连接相对较宽的迹线部分。

10. 发明授权

US10382021B2 Flexible ripple mode device implementation for programmable logic devices 有权
公开(公告)号：US10382021B2
公开(公告)日：2019-08-13
申请号：US15658349
申请日：2017-07-24
申请人： Lattice Semiconductor Corporation
发明人： Brad Sharpe-Geisler , Senani Gunaratna , Ting Yew
IPC分类号： H03K3/3562 , H03K19/00 , H03K19/173 , G06F17/50 , H03K19/177 , H03K3/356
摘要： Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.

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