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1. 发明授权

US08966329B2 Fast parallel test of SRAM arrays 有权
标题翻译： SRAM阵列的快速并行测试
公开(公告)号：US08966329B2
公开(公告)日：2015-02-24
申请号：US13808438
申请日：2011-07-19
申请人： Lawrence T. Clark , Yu Cao
发明人： Lawrence T. Clark , Yu Cao
IPC分类号： G11C29/00 , G11C29/08 , G11C29/28 , G11C29/40 , G11C11/41 , G11C29/12 , G11C29/26
CPC分类号： G11C29/08 , G11C11/41 , G11C29/28 , G11C29/40 , G11C2029/1202 , G11C2029/1204 , G11C2029/2602
摘要： In general, each parallel test operation on Static Random Access Memory (SRAM) cells is a test operation performed on a block of the SRAM cells in parallel, or simultaneously. In one embodiment, the SRAM cells are arranged into multiple rows and multiple columns where the columns are further arranged into one or more column groups. The block of the SRAM cells for each parallel test operation includes SRAM cells in two or more of the rows, SRAM cells in two or more columns in the same column group, or both SRAM cells in two or more rows and SRAM cells in two or more columns in the same column group.
摘要翻译：通常，静态随机存取存储器（SRAM）单元上的每个并行测试操作是对SRAM单元的块并行或同时执行的测试操作。在一个实施例中，SRAM单元被布置成多行和多列，其中列进一步布置成一个或多个列组。用于每个并行测试操作的SRAM单元的块包括两行或多行中的SRAM单元，同一列组中的两列或更多列中的SRAM单元，或两行或多行中的两个SRAM单元或两个或更多行中的SRAM单元更多列在同一列组中。

2. 发明申请

US20130111282A1 FAST PARALLEL TEST OF SRAM ARRAYS 有权
标题翻译： SRAM阵列的快速并行测试
公开(公告)号：US20130111282A1
公开(公告)日：2013-05-02
申请号：US13808438
申请日：2011-07-19
申请人： Lawrence T. Clark , Yu Cao
发明人： Lawrence T. Clark , Yu Cao
IPC分类号： G11C29/08
CPC分类号： G11C29/08 , G11C11/41 , G11C29/28 , G11C29/40 , G11C2029/1202 , G11C2029/1204 , G11C2029/2602
摘要： Systems and methods for performing parallel test operations on Static Random Access Memory (SRAM) cells are disclosed. In general, each parallel test operation is a test operation performed on a block of the SRAM cells in parallel, or simultaneously. In one embodiment, the SRAM cells are arranged into multiple rows and multiple columns where the columns are further arranged into one or more column groups. The block of the SRAM cells for each parallel test operation includes SRAM cells in two or more of the rows, SRAM cells in two or more columns in the same column group, or both SRAM cells in two or more rows and SRAM cells in two or more columns in the same column group.
摘要翻译：公开了用于在静态随机存取存储器（SRAM）单元上执行并行测试操作的系统和方法。通常，每个并行测试操作是对SRAM单元的块并行或同时执行的测试操作。在一个实施例中，SRAM单元被布置成多行和多列，其中列进一步布置成一个或多个列组。用于每个并行测试操作的SRAM单元的块包括两行或多行中的SRAM单元，同一列组中的两列或更多列中的SRAM单元，或两行或多行中的两个SRAM单元或两个或更多行中的SRAM单元更多列在同一列组中。

3. 发明申请

US20180046580A1 MULTI-MODE RADIATION HARDENED MULTI-CORE MICROPROCESSORS 审中-公开
公开(公告)号：US20180046580A1
公开(公告)日：2018-02-15
申请号：US15672810
申请日：2017-08-09
申请人： Lawrence T. Clark
发明人： Lawrence T. Clark
IPC分类号： G06F12/0897
摘要： Systems and methods for multi-mode radiation hardened multi-core microprocessors are disclosed. In some embodiments, a triplicated circuit includes a first core logic, a second core logic, a third core logic, and bus arbitration and control circuitry. The triplicated circuit is configurable to operate in both a Triple-Modular Redundant (TMR) mode of operation and a multi-threaded mode of operation. In some embodiments, there is essentially no overhead in soft mode and low overhead (power only) in hard mode. In most applications, it is expected that portions of missions require very hard systems (e.g., landing) where a failure is catastrophic. However, other portions require essentially no hardening (digital signal processor and signal processing activities) but much better throughput. Consequently, there is a huge opportunity to develop computer processors with low overhead in soft mode and unprecedented hardness in hard mode.

4. 发明申请

US20160065243A1 RADIATION HARDENING ARCHITECTURAL EXTENSIONS FOR A RADIATION HARDENED BY DESIGN MICROPROCESSOR 审中-公开
标题翻译：通过设计微处理器硬化辐射的辐射硬化结构扩展
公开(公告)号：US20160065243A1
公开(公告)日：2016-03-03
申请号：US14837361
申请日：2015-08-27
申请人： Dan Wheeler Patterson , Lawrence T. Clark
发明人： Dan Wheeler Patterson , Lawrence T. Clark
IPC分类号： H03M13/11 , G06F9/30 , H03M13/00
CPC分类号： G06F9/30145 , G06F9/3861 , G06F9/3863 , G06F11/00
摘要： This disclosure relates generally to processors and methods of operating the same. In particular, this disclosure relates to components for correcting soft errors in a processor. In one embodiment, a processor includes an instruction decoder and an exception handler. The instruction decoder is configured to receive one or more soft error correction instructions and decode the one or more soft error correction instructions. Additionally, an exception handler is configured to execute the one or more soft error correction instructions so as to correct one or more soft errors. In this manner, the processor is capable of correcting soft errors that are the result of radiation strikes.
摘要翻译：本公开一般涉及其操作处理器和方法。特别地，本公开涉及用于校正处理器中的软错误的组件。在一个实施例中，处理器包括指令解码器和异常处理程序。指令解码器被配置为接收一个或多个软错误校正指令并对一个或多个软错误校正指令进行解码。此外，异常处理程序被配置为执行一个或多个软错误校正指令，以便校正一个或多个软错误。以这种方式，处理器能够校正作为辐射打击结果的软错误。

5. 发明授权

US09038012B2 Sequential state elements in triple-mode redundant (TMR) state machines 有权
标题翻译：三模冗余（TMR）状态机中的顺序状态元素
公开(公告)号：US09038012B2
公开(公告)日：2015-05-19
申请号：US14304155
申请日：2014-06-13
申请人： Lawrence T. Clark , Nathan D. Hindman , Dan Wheeler Patterson
发明人： Lawrence T. Clark , Nathan D. Hindman , Dan Wheeler Patterson
IPC分类号： G06F17/50 , H03K19/173 , H03K19/003
CPC分类号： G06F17/5072 , G06F17/505 , H03K19/00315
摘要： The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.
摘要翻译：本公开一般涉及形成为诸如CMOS的半导体衬底上的集成电路的三冗余顺序状态（TRSS）机器，以及设计三重冗余顺序状态机的计算机化方法和系统。本公开中特别关注的是用于采样和保持位状态的顺序状态元素（SSE）。位状态的采样和保持由时钟信号同步，从而允许在TRSS机器中流水线化。具体地，时钟信号可以在第一时钟状态和第二时钟状态之间振荡，以根据由时钟状态提供的定时使SSE的操作同步。 SSEs具有自我纠正机制，可防止辐射诱发的软错误。 SSE可以设置在TRSS机器的管线电路中，以接收和存储由管线电路内的组合电路产生的位信号的位状态。

6. 发明授权

US08995204B2 Circuit devices and methods having adjustable transistor body bias 有权
标题翻译：具有可调节晶体管体偏置的电路器件和方法
公开(公告)号：US08995204B2
公开(公告)日：2015-03-31
申请号：US13167625
申请日：2011-06-23
申请人： Lawrence T. Clark , Bruce McWilliams , Robert Rogenmoser
发明人： Lawrence T. Clark , Bruce McWilliams , Robert Rogenmoser
IPC分类号： G11C7/00 , G11C11/412
CPC分类号： G11C11/412
摘要： Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.
摘要翻译：公开了电路，集成电路器件和方法，其可以包括具有位于栅极下方的屏蔽区域并通过半导体层与栅极分离的可偏置晶体管。偏置电压可以应用于这样的屏蔽区域以优化多个性能特征，例如速度和电流泄漏。特定实施例可以包括耦合在高电源电压和低电源电压之间的偏置部分，每个具有可偏置晶体管。一个或多个发电电路可以产生多个偏置电压。偏置控制部分可以将不同偏置电压之一耦合到可偏置晶体管的屏蔽区域，以提供用于这种最小速度的最小速度和最小电流泄漏。

7. 发明授权

US08860197B2 Integrated circuits secure from invasion and methods of manufacturing the same 有权
标题翻译：集成电路不受侵袭和制造方法
公开(公告)号：US08860197B2
公开(公告)日：2014-10-14
申请号：US13139955
申请日：2009-12-29
申请人： Lawrence T. Clark , David R. Allee
发明人： Lawrence T. Clark , David R. Allee
IPC分类号： H01L23/02 , H01L23/06 , H01L29/06 , H01L21/56 , H01L23/31 , H01L23/00 , H01L23/13 , G06F21/79 , G06F21/87 , H01L23/498
CPC分类号： H01L23/3121 , G06F21/79 , G06F21/87 , H01L21/56 , H01L23/13 , H01L23/49833 , H01L23/57 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/49 , H01L29/0657 , H01L2224/05554 , H01L2224/13099 , H01L2224/16 , H01L2224/451 , H01L2224/48091 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01049 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2224/0401 , H01L2924/00012
摘要： An integrated circuit device that is secure from invasion and related methods are disclosed herein. Other embodiments are also disclosed herein.
摘要翻译：本文公开了一种防止侵入和相关方法的集成电路装置。本文还公开了其它实施例。

8. 发明授权

US08732490B1 Methods and apparatus to selectively power functional units 有权
标题翻译：选择性地为功能单元供电的方法和装置
公开(公告)号：US08732490B1
公开(公告)日：2014-05-20
申请号：US13362358
申请日：2012-01-31
申请人： Dennis M. O'Connor , Michael W. Morrow , Lawrence T. Clark
发明人： Dennis M. O'Connor , Michael W. Morrow , Lawrence T. Clark
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3287 , G06F9/3802 , G06F9/3808 , G06F9/3814 , G06F9/382 , G06F9/3836 , G06F9/3885 , G06F12/0875 , G06F2212/1028 , Y02D10/13 , Y02D10/171
摘要： A processing engine fetches one or more lines of software instructions into an instruction cache. Based on the contents of the cache, potentially needed functional units are identified as functional units that are operable to execute at least one software instruction stored within the instruction cache. Unneeded functional units are identified as functional units that are not operable to execute a software instruction stored within the instruction cache. A power increase is initiated for selected ones of the potentially needed functional units that are determined to be in a low power state. A power decrease is initiated for selected ones of the unneeded functional units that are determined to be in an operable power state.
摘要翻译：处理引擎将一行或多行软件指令读取到指令高速缓存中。基于高速缓存的内容，可能需要的功能单元被识别为可操作以执行存储在指令高速缓存内的至少一个软件指令的功能单元。不需要的功能单元被识别为不能用于执行存储在指令高速缓存内的软件指令的功能单元。对被确定为处于低功率状态的潜在需要的功能单元中的所选择的功能单元启动功率增加。对被确定为处于可操作功率状态的不需要的功能单元中的所选功能单元启动功率减小。

9. 发明申请

US20120230087A1 SRAM CIRCUITS FOR CIRCUIT IDENTIFICATION USING A DIGITAL FINGERPRINT 有权
标题翻译：用于使用数字指纹识别电路的SRAM电路
公开(公告)号：US20120230087A1
公开(公告)日：2012-09-13
申请号：US13415599
申请日：2012-03-08
申请人： Srivatsan Chellappa , Lawrence T. Clark
发明人： Srivatsan Chellappa , Lawrence T. Clark
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C5/005
摘要： Circuitry that includes static random access memory (SRAM) access circuitry and a group of SRAM memory cells is disclosed. A digital fingerprint of the group of SRAM memory cells is determined by using the SRAM access circuitry to force at least a portion of the group of SRAM memory cells into a metastable state and then releasing the portion of the SRAM memory cells. Each SRAM memory cell that was released then selects one of two stable states and the SRAM access circuitry provides a selection profile based on the selections. The digital fingerprint is based on the selection profile.
摘要翻译：公开了包括静态随机存取存储器（SRAM）存取电路和一组SRAM存储器单元的电路。通过使用SRAM访问电路来确定SRAM存储器单元组的数字指纹，以迫使该组SRAM存储器单元的至少一部分进入亚稳态，然后释放SRAM存储单元的一部分。然后，释放的每个SRAM存储单元选择两种稳定状态之一，SRAM访问电路根据选择提供选择配置文件。数字指纹是基于选择配置文件。

10. 发明申请

US20120070158A1 FLEXIBLE IDENTIFICATION SYSTEMS AND RELATED METHODS 有权
标题翻译：灵活识别系统及相关方法
公开(公告)号：US20120070158A1
公开(公告)日：2012-03-22
申请号：US13306750
申请日：2011-11-29
申请人： David R. Allee , Lawrence T. Clark , Terry L. Alford , Constantine A. Balanis , James T. Aberle , Kevin Baugh
发明人： David R. Allee , Lawrence T. Clark , Terry L. Alford , Constantine A. Balanis , James T. Aberle , Kevin Baugh
IPC分类号： H04L27/04 , H04B1/69 , H04B10/04 , H04L27/00
CPC分类号： G06K19/07766 , G06K19/025 , G06K19/027 , H04W52/0235
摘要： Embodiments of flexible identification systems are described herein. Other embodiments and related methods are also disclosed herein.
摘要翻译：本文描述了灵活识别系统的实施例。本文还公开了其它实施例和相关方法。

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