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1. 发明授权

US09065709B1 Digital radio data system receiver methods and apparatus 有权
标题翻译：数字无线电数据系统接收机的方法和装置
公开(公告)号：US09065709B1
公开(公告)日：2015-06-23
申请号：US14076129
申请日：2013-11-08
申请人： Marvell International Ltd.
发明人： Jungwon Lee , Dimitrios-Alexandros Toumpakaris , Hui-Ling Lou , Chris Cheng-Chieh Lee
IPC分类号： H04B1/16 , H04L27/233
CPC分类号： H04L27/2334 , H04B1/1653 , H04H20/34 , H04H40/18 , H04H2201/13
摘要： Methods and apparatus are provided for receiving a first signal and generating an output signal indicative of radio data system (“RDS”) information. A receiver circuit of the invention can include mixer circuitry, lowpass filter circuitry, downsampler circuitry, and decoder circuitry. Advantageously, the receiver circuit can operate entirely within the digital domain, promoting interoperability with digital frequency modulation (“FM”) demodulator circuitry.
摘要翻译：提供了用于接收第一信号并产生指示无线电数据系统（“RDS”）信息的输出信号的方法和装置。本发明的接收机电路可以包括混频器电路，低通滤波器电路，下采样器电路和解码器电路。有利地，接收器电路可以完全在数字域内操作，促进与数字频率调制（“FM”）解调器电路的互操作性。

2. 发明授权

US08594574B1 Digital radio data system receiver methods and apparatus 有权
公开(公告)号：US08594574B1
公开(公告)日：2013-11-26
申请号：US13681200
申请日：2012-11-19
申请人： Marvell International Ltd.
发明人： Jungwon Lee , Dimitrios-Alexandros Toumpakaris , Hui-Ling Lou , Chris Cheng-Chieh Lee
IPC分类号： H04B1/16
CPC分类号： H04L27/2334 , H04B1/1653 , H04H20/34 , H04H40/18 , H04H2201/13
摘要： Methods and apparatus are provided for receiving a first signal and generating an output signal indicative of radio data system (“RDS”) information. A receiver circuit of the invention can include mixer circuitry, lowpass filter circuitry, downsampler circuitry, and decoder circuitry. Advantageously, the receiver circuit can operate entirely within the digital domain, promoting interoperability with digital frequency modulation (“FM”) demodulator circuitry.

3. 发明授权

US08619841B1 Transceiver with carrier frequency offset based parameter adjustment 有权
标题翻译：基于载波频率偏移的收发器参数调整
公开(公告)号：US08619841B1
公开(公告)日：2013-12-31
申请号：US13675516
申请日：2012-11-13
申请人： Marvell International Ltd.
发明人： Jungwon Lee , Hui-Ling Lou , Dimitrios-Alexandros Toumpakaris
IPC分类号： H04B1/38 , H04L25/02 , H04L27/00 , H04L7/00 , H04L23/00
CPC分类号： H04L27/2657 , H04B7/01
摘要： A transceiver configured to be implemented in a first device includes transmitter and receiver modules and first and second estimator modules. The receiver module receives a first signal transmitted on a channel from a second device to the first device. The first estimator module estimates a first parameter associated with the first signal or the channel. The second estimator module estimates a carrier frequency offset based on the first parameter. The carrier frequency offset is a difference between a first carrier frequency of the first device, and a second carrier frequency of the second device. The transmitter module adjusts a second parameter based on the carrier frequency offset, and based on the second parameter, transmits a second signal to the second device or the receiver module adjusts a third parameter based on the carrier frequency offset, and based on the third parameter, receives a third signal from the second device.
摘要翻译：被配置为在第一设备中实现的收发器包括发射器和接收器模块以及第一和第二估计器模块。接收器模块接收在从第二设备到第一设备的信道上发送的第一信号。第一估计器模块估计与第一信号或通道相关联的第一参数。第二估计器模块基于第一参数估计载波频率偏移。载波频率偏移是第一装置的第一载波频率和第二装置的第二载波频率之间的差。发射机模块基于载波频率偏移来调整第二参数，并且基于第二参数，将第二信号发送到第二设备，或者接收机模块基于载波频率偏移来调整第三参数，并且基于第三参数从第二设备接收第三信号。

4. 发明授权

US09065473B1 Soft decoding of coded bit-streams 有权
标题翻译：编码比特流的软解码
公开(公告)号：US09065473B1
公开(公告)日：2015-06-23
申请号：US14321442
申请日：2014-07-01
申请人： MARVELL INTERNATIONAL LTD.
发明人： Hui-Ling Lou , Dimitrios-Alexandros Toumpakaris , Jungwon Lee
IPC分类号： H03M7/46
CPC分类号： H03M7/46 , H04L1/0054 , H04L1/006 , H04L1/0067 , H04L1/0071 , H04L27/34
摘要： Systems and techniques for decoding are described. A described technique includes receiving coded bit streams that are differently encoded versions of an original bit stream, the coded bit streams including coded bits that are based on the original bit stream, where the coded bit streams have different encoding rates; identifying, within the coded bit streams, repeated coded bits of a coded bit of the coded bits that has been repeated N times; combining the coded bit streams to produce a combined bit stream by at least combining the repeated coded bits into a combined coded bit; determining, without multiplying by a normalization factor that is based on N, a bit metric for the combined coded bit that is a function of N; and decoding the combined bit stream by at least using the bit metric.
摘要翻译：描述用于解码的系统和技术。所描述的技术包括接收原始比特流的不同编码版本的编码比特流，编码比特流包括基于原始比特流的编码比特，其中编码比特流具有不同的编码率; 在编码比特流内识别重复N次的编码比特的编码比特的重复编码比特; 通过至少将重复的编码比特组合成组合的编码比特来组合编码比特流以产生组合比特流; 在不相乘基于N的归一化因子的情况下，确定作为N的函数的组合编码比特的比特度量; 以及至少使用所述比特度量对所述组合比特流进行解码。

5. 发明授权

US09209837B1 Methods, algorithms, software, circuits, receivers and systems for decoding convolutional code 有权
标题翻译：用于解码卷积码的方法，算法，软件，电路，接收器和系统
公开(公告)号：US09209837B1
公开(公告)日：2015-12-08
申请号：US13871520
申请日：2013-04-26
申请人： Marvell International Ltd.
发明人： Kok-Wui Cheong , Dimitrios-Alexandros Toumpakaris , Hui-Ling Lou
IPC分类号： H03M13/03 , H03M13/39 , H03M13/41
CPC分类号： H03M13/3972 , H03M13/3961 , H03M13/3994 , H03M13/413
摘要： Methods, software, circuits and systems involving a low complexity, tailbiting decoder. In various embodiments, the method relates to concatenating an initial and/or terminal subblock of the serial data block and outputting decoded data from an internal block of the modified data block. The circuitry generally includes a buffer, logic configured to concatenate an initial and/or terminal subblock to the serial data block, and a decoder configured to decode the data block, estimate starting and ending states for the data block, and output an internal portion of the serial data block and the one or more sequences as decoded data. The invention advantageously reduces the complexity of a suboptimal convolutional decoder, ensures smooth transitions at the beginning and end of the serial data block during decoding, and increases the reliability of the starting and ending states, without adding overhead to the transmitted data block.
摘要翻译：方法，软件，电路和系统涉及低复杂度的尾随解码器。在各种实施例中，该方法涉及连接串行数据块的初始和/或末端子块并从修改的数据块的内部块输出解码数据。电路通常包括缓冲器，被配置为将初始和/或末端子块连接到串行数据块的逻辑，以及被配置为对数据块进行解码的解码器，估计数据块的开始和结束状态，以及输出数据块的内部部分串行数据块和一个或多个序列作为解码数据。本发明有利地降低了次优卷积解码器的复杂度，确保了解码过程中串行数据块开始和结束时的平滑过渡，并增加了起始和结束状态的可靠性，而不会增加传输数据块的开销。

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