专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10193558B2 Clock signal and supply voltage variation tracking 有权
公开(公告)号：US10193558B2
公开(公告)日：2019-01-29
申请号：US15628260
申请日：2017-06-20
申请人： Micron Technology, Inc.
发明人： Yantao Ma , Tyler Gomm
IPC分类号： H03L1/00 , H03L7/08 , H03L7/081 , H03L7/089 , H03K5/156
摘要： Embodiments disclosed herein provide an apparatus comprising a clock generation circuit configured to generate a first signal for a first time period and a second signal for a second time period, a charge pump circuit coupled to the clock generation circuit and configured to generate a first voltage and a second voltage based, at least in part, on the first time period and the second time period, and a comparison circuit coupled to the charge pump circuit, the comparison circuit configured to compare a difference between the first voltage and the second voltage with a threshold value and generate an active tracking enablement signal in response to determining that the difference between the first and second voltages exceeds the threshold value.

2. 发明申请

US20170288682A1 CLOCK SIGNAL AND SUPPLY VOLTAGE VARIATION TRACKING 审中-公开
公开(公告)号：US20170288682A1
公开(公告)日：2017-10-05
申请号：US15628260
申请日：2017-06-20
申请人： Micron Technology, Inc.
发明人： Yantao Ma , Tyler Gomm
IPC分类号： H03L7/08 , H03L7/089 , H03L7/081 , H03K5/156
CPC分类号： H03L7/0802 , H03K5/1565 , H03L1/00 , H03L7/0812 , H03L7/0891
摘要： Embodiments disclosed herein provide an apparatus comprising a clock generation circuit configured to generate a first signal for a first time period and a second signal for a second time period, a charge pump circuit coupled to the clock generation circuit and configured to generate a first voltage and a second voltage based, at least in part, on the first time period and the second time period, and a comparison circuit coupled to the charge pump circuit, the comparison circuit configured to compare a difference between the first voltage and the second voltage with a threshold value and generate an active tracking enablement signal in response to determining that the difference between the first and second voltages exceeds the threshold value.

3. 发明申请

US20140375329A1 APPARATUS AND METHODS FOR DELAY LINE TESTING 有权
标题翻译：延迟线测试的装置和方法
公开(公告)号：US20140375329A1
公开(公告)日：2014-12-25
申请号：US13924231
申请日：2013-06-21
申请人： Micron Technology, Inc.
发明人： Scott Van De Graaff , Tyler Gomm , Brandon Roth , Eric Becker
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/31703
摘要： This disclosure relates to delay line test circuits and methods. In one aspect, an integrated circuit (IC) can include a plurality of delay lines, a selection circuit, a delay comparison circuit, and a control circuit. The plurality of delay lines can generate a plurality of delayed clock signals, and the selection circuit can include a plurality of inputs configured to receive at least the plurality of delayed clock signals. The selection circuit can generate a first output clock signal and a second output clock signal by selecting amongst signals received at the plurality of inputs based on a state of a selection control signal. The delay comparison circuit can compare a delay of the first output clock signal to a delay of the second output clock signal and can generate a delay comparison such as a pass/fail flag based on the result. The control circuit can generate the selection control signal.
摘要翻译：本公开涉及延迟线测试电路和方法。一方面，集成电路（IC）可以包括多个延迟线，选择电路，延迟比较电路和控制电路。多个延迟线可以产生多个延迟的时钟信号，并且选择电路可以包括被配置为至少接收多个延迟的时钟信号的多个输入。选择电路可以基于选择控制信号的状态，在多个输入端接收到的信号之间选择第一输出时钟信号和第二输出时钟信号。延迟比较电路可以将第一输出时钟信号的延迟与第二输出时钟信号的延迟进行比较，并且可以基于结果生成诸如通过/失败标志的延迟比较。控制电路可以产生选择控制信号。

4. 发明授权

US10355698B2 Clock circuits and apparatus containing such 有权
公开(公告)号：US10355698B2
公开(公告)日：2019-07-16
申请号：US14258522
申请日：2014-04-22
申请人： MICRON TECHNOLOGY, INC.
发明人： Tyler Gomm , Gary Johnson
IPC分类号： H03L7/06 , H03L7/08 , H03L7/081 , G11C7/22
摘要： Clock circuits and apparatus containing such are useful in clock synchronization and skew adjustment. Such clock circuits may include a delay line coupled to receive an input signal, wherein the delay line comprises a plurality of delay elements, and wherein at least two delay elements of the plurality of delay elements differ in unit time delay. Such clock circuits may further include a phase detector coupled to receive the input signal and a signal generated from an output signal of the delay line. The phase detector may be configured to compare the input signal to the generated signal and to adjust a length of the delay line to synchronize the input signal and the generated signal.

5. 发明申请

US20160277015A1 TWO-STAGE PHASE MIXER CIRCUIT 有权
标题翻译：两级相位混合电路
公开(公告)号：US20160277015A1
公开(公告)日：2016-09-22
申请号：US14661992
申请日：2015-03-18
申请人： Micron Technology, Inc.
发明人： YANTAO MA , Tyler Gomm
IPC分类号： H03K5/156
CPC分类号： H03K5/1565
摘要： Apparatuses and methods are directed to preventing duty cycle distortion in an electronic apparatus. The apparatus generally includes a first phase mixer stage configured to interpolate a first and a second input signal to provide a first intermediate signal and further configured to interpolate the second input signal and a third input signal to provide a second intermediate signal, the first phase mixer stage distorting duty cycle in providing the first intermediate signal. The apparatus further includes a second phase mixer stage configured to interpolate the first intermediate signal and the second intermediate signal to provide an output signal and further configured to compensate for duty cycle distortion of the first phase mixer stage.
摘要翻译：设备和方法旨在防止电子设备中的占空比变形。该装置通常包括第一相混频器级，其被配置为内插第一和第二输入信号以提供第一中间信号，并且还被配置为内插第二输入信号和第三输入信号以提供第二中间信号，第一相位混频器提供第一中间信号的阶段失真占空比。该装置还包括第二相位混频器级，其被配置为内插第一中间信号和第二中间信号以提供输出信号，并进一步被配置为补偿第一相混频器级的占空比失真。

6. 发明申请

US20150130521A1 METHOD, CIRCUIT AND SYSTEM FOR DETECTING A LOCKED STATE OF A CLOCK SYNCHRONIZATION CIRCUIT 审中-公开
标题翻译：用于检测时钟同步电路的锁定状态的方法，电路和系统
公开(公告)号：US20150130521A1
公开(公告)日：2015-05-14
申请号：US14599265
申请日：2015-01-16
申请人： Micron Technology, Inc.
发明人： Tyler Gomm , Kang Yong Kim , Scott Smith , Jongtae Kwak
IPC分类号： H03L7/08
CPC分类号： H03L7/08 , H03L7/0802 , H03L7/0812 , H03L7/095
摘要： Locked state detection circuits, devices, systems, and methods for detecting a locked or synchronized state of a clock synchronization circuit are described. Detection of a locked state includes a circuit including a phase detector configured to generate a delay adjustment signal in response to comparison of a forward path signal indicative of an external clock signal and a feedback path signal indicative of an output clock signal. The circuit further includes a trend detector operably coupled to the delay adjustment signal and configured to generate a locked signal indicative of an in-phase steady-state between the external clock signal and the output clock signal.
摘要翻译：描述了用于检测时钟同步电路的锁定或同步状态的锁定状态检测电路，设备，系统和方法。检测锁定状态包括电路，该电路包括相位检测器，该相位检测器被配置为响应于表示外部时钟信号的前向路径信号与表示输出时钟信号的反馈路径信号的比较而产生延迟调整信号。电路还包括可操作地耦合到延迟调整信号并被配置为产生指示外部时钟信号和输出时钟信号之间的同相稳态的锁定信号的趋势检测器。

7. 发明授权

US08917132B2 Apparatuses, methods, and circuits including a delay circuit 有权
标题翻译：包括延迟电路的装置，方法和电路
公开(公告)号：US08917132B2
公开(公告)日：2014-12-23
申请号：US13793627
申请日：2013-03-11
申请人： Micron Technology, Inc.
发明人： Yantao Ma , Tyler Gomm
IPC分类号： H03H11/26
CPC分类号： H03L7/085 , G11C7/222 , H03H11/265 , H03K5/14 , H03L7/0818
摘要： Apparatuses, methods, and delay circuits for delaying signals are described. An example apparatus includes a fine delay circuit configured to provide an output signal based on a ratio of a first input signal and a second input signal. The fine delay circuit including a phase mixer circuit including first signal drivers configured to receive the first input signal. The fine delay circuit further including second signal drivers configured to receive the second input signal, where at least two of the first signal drivers have different drive strengths and at least two of the second signal drivers have different drive strengths.
摘要翻译：描述用于延迟信号的装置，方法和延迟电路。示例性装置包括精细延迟电路，其被配置为基于第一输入信号和第二输入信号的比率来提供输出信号。该微型延迟电路包括相位混合电路，该相位混合电路包括被配置为接收第一输入信号的第一信号驱动器。精细延迟电路还包括被配置为接收第二输入信号的第二信号驱动器，其中至少两个第一信号驱动器具有不同的驱动强度，并且至少两个第二信号驱动器具有不同的驱动强度。

8. 发明授权

US09584140B2 Apparatuses, methods, and circuits including a delay circuit 有权
标题翻译：包括延迟电路的装置，方法和电路
公开(公告)号：US09584140B2
公开(公告)日：2017-02-28
申请号：US14576614
申请日：2014-12-19
申请人： MICRON TECHNOLOGY, INC.
发明人： Yantao Ma , Tyler Gomm
IPC分类号： H03L7/06 , H03L7/085 , G11C7/22 , H03H11/26 , H03L7/081 , H03K5/14
CPC分类号： H03L7/085 , G11C7/222 , H03H11/265 , H03K5/14 , H03L7/0818
摘要： Apparatuses, methods, and delay circuits for delaying signals are described. An example apparatus includes a fine delay circuit configured to provide an output signal based on a ratio of a first input signal and a second input signal. The fine delay circuit including a phase mixer circuit including first signal drivers configured to receive the first input signal. The fine delay circuit further including second signal drivers configured to receive the second input signal, where at least two of the first signal drivers have different drive strengths and at least two of the second signal drivers have different drive strengths.
摘要翻译：描述用于延迟信号的装置，方法和延迟电路。示例性装置包括精细延迟电路，其被配置为基于第一输入信号和第二输入信号的比率来提供输出信号。该微型延迟电路包括相位混合电路，该相位混合电路包括被配置为接收第一输入信号的第一信号驱动器。精细延迟电路还包括被配置为接收第二输入信号的第二信号驱动器，其中至少两个第一信号驱动器具有不同的驱动强度，并且至少两个第二信号驱动器具有不同的驱动强度。

9. 发明授权

US09331702B2 Apparatuses and methods for compensating for power supply sensitivities of a circuit in a clock path 有权
公开(公告)号：US09331702B2
公开(公告)日：2016-05-03
申请号：US14622031
申请日：2015-02-13
申请人： MICRON TECHNOLOGY, INC.
发明人： Yantao Ma , Tyler Gomm
IPC分类号： G11C7/00 , H03L7/08 , G11C7/22 , H03L7/081
CPC分类号： H03L7/0802 , G11C7/222 , H03L7/0812 , H03L2207/04
摘要： Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. Another example method includes providing an output clock signal in phase with an input clock signal and compensating for delay error between delays used in providing at least some of the delay of the output clock signal relative to the input clock signal by providing delays having power supply sensitivities resulting in a combined power supply sensitivity that is inverse to the delay error.

10. 发明申请

US20140293713A1 CLOCK CIRCUITS AND APPARATUS CONTAINING SUCH 审中-公开
标题翻译：时钟电路和包含这样的设备
公开(公告)号：US20140293713A1
公开(公告)日：2014-10-02
申请号：US14258522
申请日：2014-04-22
申请人： MICRON TECHNOLOGY, INC.
发明人： Tyler Gomm , Gary Johnson
IPC分类号： H03L7/08 , G11C7/22
CPC分类号： H03L7/08 , G11C7/222 , H03L7/0812
摘要： Clock circuits and apparatus containing such are useful in clock synchronization and skew adjustment. Such clock circuits may include a delay line coupled to receive an input signal, wherein the delay line comprises a plurality of delay elements, and wherein at least two delay elements of the plurality of delay elements differ in unit time delay. Such clock circuits may further include a phase detector coupled to receive the input signal and a signal generated from an output signal of the delay line. The phase detector may be configured to compare the input signal to the generated signal and to adjust a length of the delay line to synchronize the input signal and the generated signal.
摘要翻译：时钟电路和包含其的装置在时钟同步和偏斜调整中是有用的。这样的时钟电路可以包括耦合以接收输入信号的延迟线，其中延迟线包括多个延迟元件，并且其中多个延迟元件中的至少两个延迟元件在单位时间延迟上不同。这样的时钟电路还可以包括耦合以接收输入信号的相位检测器和从延迟线的输出信号产生的信号。相位检测器可以被配置为将输入信号与产生的信号进行比较，并且调整延迟线的长度以使输入信号和产生的信号同步。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式