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1. 发明授权

US11475954B2 Fast interval read setup for 3D NAND flash 有权
公开(公告)号：US11475954B2
公开(公告)日：2022-10-18
申请号：US17153525
申请日：2021-01-20
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Han-Sung Chen , Chung-Kuang Chen
IPC分类号： G11C16/04 , G11C16/26 , G11C16/08 , G11C16/30 , G11C16/24 , G11C16/10
摘要： A memory having a plurality of blocks is coupled with control circuits having logic to execute a read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include respectively a plurality of sub-blocks, The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.

2. 发明授权

US09542268B2 Dynamic data density ECC 有权
标题翻译：动态数据密度ECC
公开(公告)号：US09542268B2
公开(公告)日：2017-01-10
申请号：US14167927
申请日：2014-01-29
申请人： Macronix International Co., Ltd.
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： H03M13/00 , H03M13/11 , G06F11/10 , H03M13/15 , H03M13/35
CPC分类号： G06F11/1048 , H03M13/151 , H03M13/356 , H03M13/6505 , H03M13/6561
摘要： A method for operating a memory includes receiving an input data set, saving a first level error correcting code ECC for the data in the input data set, saving second level ECCs for a plurality of second level groups of the data in the data set, storing the data set in the memory, and testing the data set to determine whether to use the first level ECC or the second level ECCs. The method includes, if the first level ECC is used, storing a flag enabling use of the first level ECC, else if the second level ECCs are used, storing a flag enabling use of the second level ECCs. The method includes storing the second level ECCs in a replacement ECC memory, and storing a pointer indicating locations of the second level ECCs in the replacement ECC memory.
摘要翻译：用于操作存储器的方法包括接收输入数据集，为输入数据集中的数据保存第一级纠错码ECC，为数据集中的数据的多个第二级组保存第二级ECC，存储存储器中的数据集，并测试数据集以确定是使用第一级ECC还是第二级ECC。该方法包括如果使用第一级ECC，则存储能够使用第一级ECC的标志，否则如果使用第二级ECC，则存储允许使用第二级ECC的标志。该方法包括将第二级ECC存储在替换ECC存储器中，并将指示第二级ECC的位置的指针存储在替换ECC存储器中。

3. 发明授权

US09536601B2 Threshold voltage grouping of memory cells in same threshold voltage range 有权
标题翻译：在相同阈值电压范围内的存储器单元的阈值电压分组
公开(公告)号：US09536601B2
公开(公告)日：2017-01-03
申请号：US14533936
申请日：2014-11-05
申请人： Macronix International Co., Ltd.
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C16/04 , G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3481 , G11C2211/5642
摘要： A memory cell undergoing programming is determined as belonging to a particular one of a plurality of second threshold voltage ranges that divide a present threshold voltage range of the particular memory cell. Programming pulses are applied to program the particular memory cell to within the target threshold voltage range. At least one of a program voltage and a total duration of the programming pulses applied to the particular memory cell is varied, depending on the particular second threshold voltage range of the memory cell.
摘要翻译：正在进行编程的存储单元被确定为属于划分特定存储单元的当前阈值电压范围的多个第二阈值电压范围中的特定的一个。施加编程脉冲以将特定存储器单元编程到目标阈值电压范围内。根据存储单元的特定的第二阈值电压范围，施加到特定存储单元的编程脉冲的编程电压和总持续时间中的至少一个是不同的。

4. 发明授权

US09508455B2 Memory device and operating method thereof for reducing interference between memory cells 有权
标题翻译：用于减少存储器单元之间的干扰的存储器件及其操作方法
公开(公告)号：US09508455B2
公开(公告)日：2016-11-29
申请号：US14595252
申请日：2015-01-13
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C7/10 , G11C29/50 , G11C29/00
CPC分类号： G11C29/50016 , G11C7/02 , G11C7/1036 , G11C11/5628 , G11C16/10 , G11C16/12 , G11C16/3427 , G11C16/3459 , G11C19/00 , G11C29/86 , G11C2211/5621
摘要： An operating method of a memory device comprises the following steps: a first page buffer receives a first input data to be programed into a first memory cell of the memory cells; a second page buffer receives a second input data to be programed into a second memory cell of the memory cells; and the first page buffer determines whether to shift a program verify (PV) voltage for the first input data according to the first and second input data.
摘要翻译：存储器件的操作方法包括以下步骤：第一页缓冲器接收要被编程到存储器单元的第一存储器单元中的第一输入数据; 第二页缓冲器接收要编程到存储器单元的第二存储单元中的第二输入数据; 并且第一页缓冲器根据第一和第二输入数据确定是否移位用于第一输入数据的程序验证（PV）电压。

5. 发明授权

US09437264B2 Memory operation latency control 有权
标题翻译：内存操作延迟控制
公开(公告)号：US09437264B2
公开(公告)日：2016-09-06
申请号：US15055329
申请日：2016-02-26
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Chun-Hsiung Hung , Han-Sung Chen , Ming-Chao Lin
IPC分类号： G11C8/08 , G11C16/30 , G11C7/22
CPC分类号： G11C7/22 , G11C5/145 , G11C8/08 , G11C16/08 , G11C16/30 , G11C2207/2272 , G11C2207/2281
摘要： An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.
摘要翻译：具有存储器的集成电路可以在诸如读取操作的连续操作之间以较低的延迟进行操作。第一次，在集成电路上的存储器阵列上完成第一操作命令。第二次，在存储器阵列上开始第二操作命令。来自电荷泵的稳定的输出电压被耦合到存储器阵列中的字线。从第一次到第二次，稳定的输出电压保持在诸如读取电压的字线操作电压。

6. 发明申请

US20160125922A1 THRESHOLD VOLTAGE GROUPING OF MEMORY CELLS IN SAME THRESHOLD VOLTAGE RANGE 有权
标题翻译：存储器电池的阈值电压分组在相同的阈值电压范围内
公开(公告)号：US20160125922A1
公开(公告)日：2016-05-05
申请号：US14533936
申请日：2014-11-05
申请人： Macronix International Co., Ltd.
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C7/10 , G11C7/08 , G11C7/12
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3481 , G11C2211/5642
摘要： A memory cell undergoing programming is determined as belonging to a particular one of a plurality of second threshold voltage ranges that divide a present threshold voltage range of the particular memory cell. Programming pulses are applied to program the particular memory cell to within the target threshold voltage range. At least one of a program voltage and a total duration of the programming pulses applied to the particular memory cell is varied, depending on the particular second threshold voltage range of the memory cell.
摘要翻译：正在进行编程的存储单元被确定为属于划分特定存储单元的当前阈值电压范围的多个第二阈值电压范围中的特定的一个。施加编程脉冲以将特定存储器单元编程到目标阈值电压范围内。根据存储单元的特定的第二阈值电压范围，施加到特定存储单元的编程脉冲的编程电压和总持续时间中的至少一个是不同的。

7. 发明授权

US09117492B2 Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits 有权
标题翻译：用于调整具有寻址和相邻位的存储单元的漏极偏置的方法和装置
公开(公告)号：US09117492B2
公开(公告)日：2015-08-25
申请号：US14556973
申请日：2014-12-01
申请人： Macronix International Co., Ltd.
发明人： Han-Sung Chen , Chung-Kuang Chen , Chun-Hsiung Hung
IPC分类号： G11C7/00 , G11C7/22 , G11C11/56
CPC分类号： G11C7/00 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C2211/5621
摘要： The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.
摘要翻译：诸如非易失性存储单元的氮化物层的存储层具有存储单独可寻址数据的两个存储部分，通常分别靠近源极端子和漏极端子。在感测一个存储部件的数据时所施加的漏极电压取决于存储在另一个存储部分的数据。如果存储在另一个存储部分的数据由超过最小阈值电压的阈值电压表示，则所施加的漏极电压升高。该技术在读取操作和程序验证操作中有助于拓宽阈值电压窗口。

8. 发明授权

US10790009B1 Sensing a memory device 有权
公开(公告)号：US10790009B1
公开(公告)日：2020-09-29
申请号：US16552153
申请日：2019-08-27
申请人： Macronix International Co., Ltd.
发明人： Chung-Kuang Chen , Han-Sung Chen
IPC分类号： G11C7/12 , G11C11/4091 , G11C7/10 , G11C11/4074 , G11C11/4094
摘要： A memory device comprises a memory cell array, a plurality of sense amplifiers and a memory controller for controlling the plurality of sense amplifiers. The memory cell array includes a plurality of bit lines, where a bit line is coupled to a plurality of memory cells. A sense amplifier is coupled to a bit line and provides a sensing current to access data from one or more memory cells of the plurality of memory cells corresponding to the bit line. The memory controller performs operations comprising: during a pre-charging stage of a memory access cycle, providing, to a particular sense amplifier, a first voltage; and during a sensing stage of the memory access cycle, providing, to the particular sense amplifier, a second voltage, where the second voltage is a non-zero voltage that is lower than the first voltage.

9. 发明授权

US09270272B2 Clock integrated circuit 有权
公开(公告)号：US09270272B2
公开(公告)日：2016-02-23
申请号：US14467419
申请日：2014-08-25
申请人： Macronix International Co., Ltd.
发明人： Chung-Kuang Chen , Chun-Hsiung Hung , Han-Sung Chen
IPC分类号： G06F1/12 , G06F1/00 , G06F1/04 , G06F3/02 , G06F3/16 , H03B5/32 , H03K19/0175 , G06F1/08 , G05F3/02 , H03L5/00 , G06F1/10
CPC分类号： H03K19/018528 , G05F3/02 , G06F1/04 , G06F1/08 , G06F1/10 , G06F1/12 , H03K19/0175 , H03L5/00
摘要： The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

10. 发明授权

US08947961B2 Management of non-volatile memory 有权
标题翻译：管理非易失性存储器
公开(公告)号：US08947961B2
公开(公告)日：2015-02-03
申请号：US13950942
申请日：2013-07-25
申请人： Macronix International Co., Ltd.
发明人： Lung Yi Kuo , Hsin Yi Ho , Chun Hsiung Hung , Shuo-Nan Hung , Han-Sung Chen , Shih-Chou Juan
IPC分类号： G11C16/04 , G11C16/06 , G11C29/00 , G11C16/10 , G11C29/04
CPC分类号： G11C16/10 , G11C29/808 , G11C29/82 , G11C2029/4402
摘要： A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged section table to determine whether the current section is damaged. The damaged section table records information about whether a section in the memory is good or damaged. The method further includes using the current section for programming if the current section is not damaged.
摘要翻译：一种用于编程包括多个块的非易失性存储器的方法，每个块包括多个部分，每个部分包括至少一个页面，并且每个页面包括多个存储器单元。该方法包括根据损坏部分表检查多个部分的当前部分，以确定当前部分是否损坏。损坏的部分表记录有关内存中的部分是好还是损坏的信息。该方法还包括如果当前部分没有损坏，则使用当前部分进行编程。

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