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1. 发明授权

US10250264B2 Multiplying delay-locked loop using sampling time-to-digital converter 有权
公开(公告)号：US10250264B2
公开(公告)日：2019-04-02
申请号：US15629427
申请日：2017-06-21
申请人： Marvell World Trade Ltd.
发明人： Haisong Wang , Olivier Burg
IPC分类号： H03L7/06 , H03L7/081 , H03L7/091
摘要： A multiplying delay-locked loop circuit includes a delay chain including a plurality of variable delay circuits connected in series and having a delay chain output, and a feedback loop including circuitry for deriving a digital control signal representing magnitude and sign of phase offset in the delay chain output, for controlling delay in ones of the variable delay circuits. The circuitry for deriving a digital control signal includes a sampling time-to-digital converter (STDC) configured to operate on a time delay between inputs to generate the digital control signal. The STDC subtracts a second difference the signals derived from the delay chain output and output of the feedback divider from a first difference between the signals derived from the delay chain output and output of the feedback divider to provide a difference value, and the difference value indicates sign and magnitude of output offset in the delay chain output.

2. 发明申请

US20170366191A1 MULTIPLYING DELAY-LOCKED LOOP USING SAMPLING TIME-TO-DIGITAL CONVERTER 审中-公开
公开(公告)号：US20170366191A1
公开(公告)日：2017-12-21
申请号：US15629427
申请日：2017-06-21
申请人： Marvell World Trade Ltd.
发明人： Haisong Wang , Olivier Burg
IPC分类号： H03L7/081 , H03L7/091
CPC分类号： H03L7/0814 , H03L7/091
摘要： A multiplying delay-locked loop circuit includes a delay chain including a plurality of variable delay circuits connected in series and having a delay chain output, and a feedback loop including circuitry for deriving a digital control signal representing magnitude and sign of phase offset in the delay chain output, for controlling delay in ones of the variable delay circuits. The circuitry for deriving a digital control signal includes a sampling time-to-digital converter (STDC) configured to operate on a time delay between inputs to generate the digital control signal. The STDC subtracts a second difference the signals derived from the delay chain output and output of the feedback divider from a first difference between the signals derived from the delay chain output and output of the feedback divider to provide a difference value, and the difference value indicates sign and magnitude of output offset in the delay chain output.

3. 发明申请

US20140218086A1 METHODS AND DEVICES FOR MULTIPLE-MODE RADIO FREQUENCY SYNTHESIZERS 有权
标题翻译：多模式无线电频率合成器的方法和设备
公开(公告)号：US20140218086A1
公开(公告)日：2014-08-07
申请号：US14244710
申请日：2014-04-03
申请人： Marvell World Trade Ltd.
发明人： Olivier Burg , Cao-Thong Tu
IPC分类号： H03L7/099
CPC分类号： H03L7/1976 , H03L7/0991 , H03L7/113 , H03L7/16 , H03L2207/50
摘要： Methods and devices provide for determining whether to operate a radio frequency synthesizer in a first mode of operation or a second mode of operation based on a reference frequency signal. The radio frequency synthesizer includes a digitally-controlled oscillator configured to generate an oscillator signal having an output frequency. A digital frequency locked-loop is configured to control the output frequency of the oscillator signal in a first mode of operation based on a first control signal. A digital phase locked-loop is configured to control the output frequency of the oscillator signal in a second mode of operation based on a second control signal. A controller determines whether to operate in the first mode or second mode based on a reference frequency signal. The controller generates the first or second control signal based on the determination of operating in the first or second mode, respectively.
摘要翻译：方法和装置提供用于基于参考频率信号来确定是否在第一操作模式或第二操作模式中操作射频合成器。射频合成器包括配置成产生具有输出频率的振荡器信号的数字控制振荡器。数字频率锁定环被配置为基于第一控制信号来控制处于第一操作模式的振荡器信号的输出频率。数字锁相环被配置为基于第二控制信号在第二操作模式中控制振荡器信号的输出频率。控制器基于参考频率信号来确定是否在第一模式或第二模式中操作。控制器基于分别在第一或第二模式中的操作的确定来产生第一或第二控制信号。

4. 发明申请

US20170366376A1 ANALOG FRACTIONAL-N PHASE-LOCKED LOOP 审中-公开
公开(公告)号：US20170366376A1
公开(公告)日：2017-12-21
申请号：US15629509
申请日：2017-06-21
申请人： Marvell World Trade Ltd.
发明人： Haisong Wang , Xiang Gao , Olivier Burg , Cao-Thong Tu
IPC分类号： H04L27/20 , H03L7/197 , H03L7/087 , H04L25/03 , H03L7/081
CPC分类号： H04L27/2017 , H03L7/081 , H03L7/087 , H03L7/093 , H03L7/1976 , H03L2207/06 , H04L25/03834 , H04L27/0014
摘要： An analog fractional-N phase-locked loop includes an oscillator loop having a reference input, a feedback input, and a loop output, and a fractional feedback divider configured to divide signals on the loop output by a divisor. Output of the fractional feedback divider is fed back to the feedback input. A compensation circuit is coupled to, and configured to apply a time delay to, the reference input or the feedback input, to compensate for delay introduced by the fractional feedback divider. The compensation circuit may be a digital-to-time converter configured to convert a digital delay signal into the time delay. The digital-to-time converter may be coupled to the reference input to delay signals to match feedback delay introduced by the fractional feedback divider, or to the feedback input to subtract the time delay to cancel feedback delay introduced by the fractional feedback divider.

5. 发明授权

US09740175B2 All-digital phase locked loop (ADPLL) including a digital-to-time converter (DTC) and a sampling time-to-digital converter (TDC) 有权
公开(公告)号：US09740175B2
公开(公告)日：2017-08-22
申请号：US15370796
申请日：2016-12-06
申请人： Marvell World Trade Ltd.
发明人： Olivier Burg , Haisong Wang , Xiang Gao
IPC分类号： H03M1/50 , G04F10/00 , H03M1/00 , H04M1/50 , H03M1/12 , H03B21/02 , H03L7/089
CPC分类号： G04F10/005 , H03B21/02 , H03L7/0891 , H03L7/091 , H03L7/0991 , H03L7/18 , H03M1/00 , H03M1/12 , H03M1/50 , H03M7/3004 , H03M2201/4233 , H04M1/505
摘要： A digital phase locked loop (DPLL) circuit includes a digital-to-time converter (DTC) configured to generate a delayed reference clock signal by delaying a reference clock signal according to a delay control signal and a time-to-digital converter (TDC) coupled to an output of the DTC. The TDC is configured to sample a value of a transition signal according to the delayed reference clock signal and to generate an output signal indicating a phase difference between the delayed clock signal and an input clock signal. A method of controlling a DPLL includes delaying a reference clock signal according to a delay control signal, sampling a value of a transition signal according to the delayed reference clock signal, generating an output signal indicating a phase difference between the delayed clock signal and an input clock signal, and generating a digitally controlled oscillator (DCO) clock signal according to the output signal.

6. 发明申请

US20150249455A1 METHODS AND DEVICES FOR IMPLEMENTING ALL-DIGITAL PHASE LOCKED LOOP 审中-公开
标题翻译：用于实现全数字锁相环的方法和装置
公开(公告)号：US20150249455A1
公开(公告)日：2015-09-03
申请号：US14713945
申请日：2015-05-15
申请人： Marvell World Trade Ltd.
发明人： Olivier Burg , Miguel Kirsch
IPC分类号： H03L7/197
CPC分类号： H03L7/1976 , H03L7/0991 , H03L7/113 , H03L7/16 , H03L2207/50
摘要： An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock. The digital processor uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew.
摘要翻译：全数字锁相环包括确定相位数的分数部分的时间到数字转换器。数字转换器的时间具有可能由相位噪声，延迟误差或偏斜误差引起的量化误差。若干方法和装置可以减少量化误差。噪声源可能在时间到数字转换器的输入处将抖动添加到参考时钟。数字处理器可以使用振荡器信号的两个连续的上升沿来计算到数字转换器到参考时钟的时间的时间延迟。数字处理器使用这些计数来确定用于控制数控振荡器的振荡器信号的时间延迟和时间周期的比率。射频计数器电路检测振荡器信号是否由于偏斜引起或滞后于参考时钟，并产生相位信号以纠正偏斜。

7. 发明授权

US09306586B2 Methods and devices for implementing all-digital phase locked loop 有权
标题翻译：用于实现全数字锁相环的方法和装置
公开(公告)号：US09306586B2
公开(公告)日：2016-04-05
申请号：US14713945
申请日：2015-05-15
申请人： Marvell World Trade Ltd.
发明人： Olivier Burg , Miguel Kirsch
IPC分类号： H03L7/197 , H03L7/113 , H03L7/16 , H03L7/099
CPC分类号： H03L7/1976 , H03L7/0991 , H03L7/113 , H03L7/16 , H03L2207/50
摘要： An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock. The digital processor uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew.
摘要翻译：全数字锁相环包括确定相位数的分数部分的时间到数字转换器。数字转换器的时间具有可能由相位噪声，延迟误差或偏斜误差引起的量化误差。若干方法和装置可以减少量化误差。噪声源可能在时间到数字转换器的输入处将抖动添加到参考时钟。数字处理器可以使用振荡器信号的两个连续的上升沿来计算到数字转换器到参考时钟的时间的时间延迟。数字处理器使用这些计数来确定用于控制数控振荡器的振荡器信号的时间延迟和时间周期的比率。射频计数器电路检测振荡器信号是否由于偏斜引起或滞后于参考时钟，并产生相位信号以纠正偏斜。

8. 发明授权

US08957713B2 Methods and devices for multiple-mode radio frequency synthesizers 有权
标题翻译：多模射频合成器的方法和装置
公开(公告)号：US08957713B2
公开(公告)日：2015-02-17
申请号：US14244710
申请日：2014-04-03
申请人： Marvell World Trade Ltd.
发明人： Olivier Burg , Cao-Thong Tu
IPC分类号： H03L7/06 , H03L7/099 , H03L7/113 , H03L7/16
CPC分类号： H03L7/1976 , H03L7/0991 , H03L7/113 , H03L7/16 , H03L2207/50
摘要： Methods and devices provide for determining whether to operate a radio frequency synthesizer in a first mode of operation or a second mode of operation based on a reference frequency signal. The radio frequency synthesizer includes a digitally-controlled oscillator configured to generate an oscillator signal having an output frequency. A digital frequency locked-loop is configured to control the output frequency of the oscillator signal in a first mode of operation based on a first control signal. A digital phase locked-loop is configured to control the output frequency of the oscillator signal in a second mode of operation based on a second control signal. A controller determines whether to operate in the first mode or second mode based on a reference frequency signal. The controller generates the first or second control signal based on the determination of operating in the first or second mode, respectively.
摘要翻译：方法和装置提供用于基于参考频率信号来确定是否在第一操作模式或第二操作模式中操作射频合成器。射频合成器包括配置成产生具有输出频率的振荡器信号的数字控制振荡器。数字频率锁定环被配置为基于第一控制信号来控制处于第一操作模式的振荡器信号的输出频率。数字锁相环被配置为基于第二控制信号在第二操作模式中控制振荡器信号的输出频率。控制器基于参考频率信号来确定是否在第一模式或第二模式中操作。控制器基于分别在第一或第二模式中的操作的确定来产生第一或第二控制信号。

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