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1. 发明授权

US07839230B2 PLL oscillation circuit, polar transmitting circuit, and communication device 失效
标题翻译： PLL振荡电路，极性发射电路和通信装置
公开(公告)号：US07839230B2
公开(公告)日：2010-11-23
申请号：US12469252
申请日：2009-05-20
申请人： Masakatsu Maeda , Takayuki Tsukizawa , Hiroyuki Yoshikawa , Shunsuke Hirano
发明人： Masakatsu Maeda , Takayuki Tsukizawa , Hiroyuki Yoshikawa , Shunsuke Hirano
IPC分类号： H03L5/00
CPC分类号： H03L7/099 , H03C3/04 , H03C3/0925 , H03C3/0933 , H03C5/00 , H03L5/00
摘要： Provided is a PLL oscillation circuit that can reduce the variability of modulation sensitivity of a VCO 101 and obtain a desired output amplitude quickly with high precision. An amplitude detector 103 detects an output amplitude of the VCO 101. An amplitude controller 105 controls a current value of a variable current source 109 so as to have an output amplitude of the VCO 101 detected by the amplitude detector 103 to be a desired amplitude. A LPF 108 is connected between the amplitude controller 105 and the variable current source 109. A switch 107 connects or disconnects the LPF 108 between the amplitude controller 105 and the variable current source 109. The amplitude controller 105 is connected to the variable current source 109 through either the LPF 108 or the switching switch 107.
摘要翻译：提供了一种PLL振荡电路，其可以降低VCO 101的调制灵敏度的可变性，并以高精度快速获得期望的输出幅度。振幅检测器103检测VCO 101的输出幅度。振幅控制器105控制可变电流源109的电流值，使振幅检测器103检测到的VCO 101的输出幅度为期望幅度。 LPF 108连接在振幅控制器105和可变电流源109之间。开关107连接或断开振幅控制器105和可变电流源109之间的LPF108。振幅控制器105连接到可变电流源109 通过LPF 108或切换开关107。

2. 发明申请

US20060115036A1 Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method 有权
$Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method$
标题翻译：配有分数部分控制电路，通信装置，调频装置和频率调制方法的频率合成装置
公开(公告)号：US20060115036A1
公开(公告)日：2006-06-01
申请号：US11333245
申请日：2006-01-18
申请人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
发明人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
IPC分类号： H03D3/24
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.
摘要翻译：包括PLL电路的频率合成器装置的分数部分控制电路是用于控制与PLL电路的可变分频器分频的分数部分的多n-Δ级Δ-Σ调制器电路。加法器将分数部分的数据与来自乘法器的输出数据相加，并将结果数据通过二阶积分器输出到量化器。量化器用量化步长量化输入数据，并通过反馈电路将量化的数据输出到乘法器。量化数据用作受控分数部分的数据。乘法器将来自反馈电路的数据乘以量化步长，并将结果数据输出到加法器。分数部分控制电路周期性地改变分数部分的数据，从而根据周期的平均值设置来自VCO的输出信号的频率。

3. 发明授权

US06717998B2 Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method 有权
$Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method$
公开(公告)号：US06717998B2
公开(公告)日：2004-04-06
申请号：US09733949
申请日：2000-12-12
申请人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
发明人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
IPC分类号： H03D324
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

4. 发明授权

US07050525B2 Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method 有权
$Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method$
公开(公告)号：US07050525B2
公开(公告)日：2006-05-23
申请号：US10728863
申请日：2003-12-08
申请人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
发明人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
IPC分类号： H03D3/24 , H03L7/00 , H03C3/06
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

5. 发明授权

US07110486B2 Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method 有权
$Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method$
公开(公告)号：US07110486B2
公开(公告)日：2006-09-19
申请号：US11333245
申请日：2006-01-18
申请人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
发明人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
IPC分类号： H03D3/24 , H03L7/00 , H03C3/06
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

6. 发明授权

US07826811B2 Phase modulation apparatus and wireless communication apparatus 有权
标题翻译：相位调制装置和无线通信装置
公开(公告)号：US07826811B2
公开(公告)日：2010-11-02
申请号：US11594979
申请日：2006-11-09
申请人： Hiroyuki Yoshikawa , Shunsuke Hirano
发明人： Hiroyuki Yoshikawa , Shunsuke Hirano
IPC分类号： H04B1/16
CPC分类号： H04L27/2092 , H03C3/0925 , H03C3/0941 , H03C3/095 , H03C5/00
摘要： A two-point modulation type phase apparatus and a wireless communication apparatus capable of achieving a reduction in circuit scale and low power consumption while maintaining modulation precision. It is possible to provide a D/A converter (150) that converts the inputted digital baseband signal to an analog signal, an adder (110) that adds an output signal of a D/A converter (150) and an output of a loop filter (135) to output to a control voltage terminal of the voltage controlled oscillator (105), and a peak control section (140) provided at a front stage of the D/A converter (150) that carries out smoothing of peak portions appearing at the inputted digital baseband signal, at a two-point modulation type phase modulation apparatus (100) that modulates a-carrier frequency signal using an inputted digital baseband signal by setting a frequency dividing ratio of a frequency divider (115) of a PLL circuit based on an inputted digital baseband modulation signal, and adding a voltage corresponding to a signal that is an inputted digital baseband signal analog-converted for supply to a control voltage terminal of a voltage controlled oscillator (105).
摘要翻译：一种两点调制型相位装置和无线通信装置，其能够在保持调制精度的同时实现电路规模的降低和低功耗。可以提供将输入的数字基带信号转换为模拟信号的D / A转换器（150），将D / A转换器（150）的输出信号和循环的输出相加的加法器（110）滤波器（135）输出到压控振荡器（105）的控制电压端，以及峰值控制部（140），设置在D / A转换器（150）的前级，其执行出现峰值部分的平滑化在输入的数字基带信号的两点调制型相位调制装置（100）中，通过设定PLL电路的分频器（115）的分频比，使用输入的数字基带信号来调制a载波频率信号基于输入的数字基带调制信号，并将与作为模拟转换的输入数字基带信号的信号相对应的电压相加，供给压控振荡器（105）的控制电压端。

7. 发明申请

US20050271159A1 Frequency modulation apparatus 失效
标题翻译：调频装置
公开(公告)号：US20050271159A1
公开(公告)日：2005-12-08
申请号：US11080680
申请日：2005-03-16
申请人： Hiroyuki Yoshikawa , Hisashi Adachi , Shunsuke Hirano
发明人： Hiroyuki Yoshikawa , Hisashi Adachi , Shunsuke Hirano
IPC分类号： H03C3/00 , H03C3/09 , H04L27/04 , H04L27/12 , H04L27/20
CPC分类号： H03C3/0933 , H03C3/0925 , H04L27/12 , H04L27/2003
摘要： A frequency modulation apparatus 100 has a synthesizer 101, a differentiator 102 that differentiates phase modulation data and generates differential phase modulation data, an adder 103 that adds together that differential phase modulation data and carrier frequency data fractional part K and generates addition fractional part K1, an input data operation section 104 that receives addition fractional part K1 and carrier frequency data integer part M, generates integer part input data M1 and fractional part input data K2, and provides fractional part input data K2 to synthesizer 101, and an integer part data delay section 105 that delays integer part input data M1 before providing it to synthesizer 101. Input data operation section 104 makes M1=M−1 and K2=K1+1 when K1
摘要翻译：频率调制装置100具有合成器101，微分器102，其对相位调制数据进行微分并产生差分相位调制数据;加法器103，将差分相位调制数据和载波频率数据小数部分K相加，生成加法分数部分K 1 ，接收加法分数部分K 1和载波频率数据整数部分M的输入数据操作部分104产生整数部分输入数据M 1和小数部分输入数据K 2，并向合成器101提供分数部分输入数据K 2，以及整数部分数据延迟部分105，其在将整数部分输入数据M 1提供给合成器101之前将其延迟。当K 1 <0时，输入数据运算部104使M 1 = M-1，K 2 = K 1 +1，当0 <= K 1 <1时，M 1 = M，K 2 = K 1，使M 1 = 1 + = 1，K 2 = K 1 -1。

8. 发明申请

US20070149148A1 Phase modulation apparatus and wireless communication apparatus 有权
标题翻译：相位调制装置和无线通信装置
公开(公告)号：US20070149148A1
公开(公告)日：2007-06-28
申请号：US11594979
申请日：2006-11-09
申请人： Hiroyuki Yoshikawa , Shunsuke Hirano
发明人： Hiroyuki Yoshikawa , Shunsuke Hirano
IPC分类号： H04B1/04 , H01Q11/12
CPC分类号： H04L27/2092 , H03C3/0925 , H03C3/0941 , H03C3/095 , H03C5/00
摘要： A two-point modulation type phase apparatus and a wireless communication apparatus capable of achieving a reduction in circuit scale and low power consumption while maintaining modulation precision. It is possible to provide a D/A converter (150) that converts the inputted digital baseband signal to an analog signal, an adder (110) that adds an output signal of a D/A converter (150) and an output of a loop filter (135) to output to a control voltage terminal of the voltage controlled oscillator (105), and a peak control section (140) provided at a front stage of the D/A converter (150) that carries out smoothing of peak portions appearing at the inputted digital baseband signal, at a two-point modulation type phase modulation apparatus (100) that modulates a-carrier frequency signal using an inputted digital baseband signal by setting a frequency dividing ratio of a frequency divider (115) of a PLL circuit based on an inputted digital baseband modulation signal, and adding a voltage corresponding to a signal that is an inputted digital baseband signal analog-converted for supply to a control voltage terminal of a voltage controlled oscillator (105).
摘要翻译：一种两点调制型相位装置和无线通信装置，其能够在保持调制精度的同时实现电路规模的降低和低功耗。可以提供将输入的数字基带信号转换为模拟信号的D / A转换器（150），将D / A转换器（150）的输出信号和循环的输出相加的加法器（110）滤波器（135）输出到压控振荡器（105）的控制电压端，以及峰值控制部（140），设置在D / A转换器（150）的前级，其执行出现峰值部分的平滑化在输入的数字基带信号的两点调制型相位调制装置（100）中，通过设定PLL电路的分频器（115）的分频比，使用输入的数字基带信号来调制a载波频率信号基于输入的数字基带调制信号，并将与作为模拟转换的输入数字基带信号的信号相对应的电压相加，供给压控振荡器（105）的控制电压端。

9. 发明申请

US20060052073A1 Wide-band modulation pll, timing error correction system of wide-band modulation pll, modulation timing error correction method and method for adjusting radio communication apparatus having wide-band modulation pll 失效
标题翻译：宽带调制pl1，宽带调制pll的定时误差校正系统，调制定时误差校正方法和调整具有宽带调制的无线通信装置的方法
公开(公告)号：US20060052073A1
公开(公告)日：2006-03-09
申请号：US10529539
申请日：2004-08-04
申请人： Hiroyuki Yoshikawa , Shunsuke Hirano
发明人： Hiroyuki Yoshikawa , Shunsuke Hirano
IPC分类号： H04B1/18
CPC分类号： H03C3/095 , H03C3/0925 , H03C3/0933 , H03C3/0941
摘要： An object of the present invention is to provide a modulation-precision enhanced broadband modulation PLL, a timing error correcting system of the broadband modulation PLL, a timing error correcting method and an adjusting method of a radio communication device having a broadband modulation PLL. There is provided a PLL portion containing a voltage controlled oscillator (101), a frequency divider (105), a phase comparator (104) and a loop filter (103). A frequency-dividing ratio of the frequency divider (105) is controlled to apply modulation, and also an input voltage of the voltage controlled oscillator (101) is controlled to apply modulation. One of phase modulation data for controlling the frequency dividing ratio and phase modulation data for input voltage of the voltage controlled oscillator (101) is inverted in phase by using an inverter (113), and the delay control circuit (110) detects a timing error on the basis of a signal (133) achieved by adding the output signals (131) and (132) of the filter (106) and the loop filter (103), and the timing is controlled by the delay circuits (111) and (112) to correct the timing error.
摘要翻译：本发明的目的是提供调制精度增强型宽带调制PLL，宽带调制PLL的定时误差校正系统，具有宽带调制PLL的无线通信装置的定时误差校正方法和调整方法。

10. 发明申请

US20050232385A1 Two-point frequency modulation apparatus, wireless transmitting apparatus, and wireless receiving apparatus 失效
标题翻译：两点式调频装置，无线发送装置以及无线接收装置
公开(公告)号：US20050232385A1
公开(公告)日：2005-10-20
申请号：US11066561
申请日：2005-02-28
申请人： Hiroyuki Yoshikawa , Shunsuke Hirano , Tatsuto Oka
发明人： Hiroyuki Yoshikawa , Shunsuke Hirano , Tatsuto Oka
IPC分类号： H03C3/09 , H03D3/24 , H03L7/18 , H03L7/197
CPC分类号： H03C3/095 , H03C3/0925 , H03C3/0933 , H03C3/0941
摘要： A two-point frequency modulation apparatus is provided that reduces input timing difference and improves modulation accuracy. Two-point frequency modulation apparatus 10 has: PLL circuit 11; frequency division ratio generator 13 that generates the frequency division ratio in frequency divider 111 based on first digital baseband signal S1 and carrier signal; adder 114 that adds second digital baseband signal S2 to the output signal of loop filter 113; a delay index calculator (filter coefficient calculator 17) that calculates the delay index based on the magnitude of change in the amplitude of the output signal of adder 114; and a delay adjuster (digital filter 18) that shifts the phase of one of first digital baseband signal S1 and second digital baseband signal S2 according to the delay index so as to reduce the phase difference.
摘要翻译：提供一种降低输入定时差并提高调制精度的两点式调频装置。两点式调频装置10具有：PLL电路11; 分频比发生器13，其基于第一数字基带信号S1和载波信号产生分频器111中的分频比; 加法器114，其将第二数字基带信号S2添加到环路滤波器113的输出信号; 延迟指数计算器（滤波器系数计算器17），其基于加法器114的输出信号的振幅的变化幅度来计算延迟指数; 以及延迟调整器（数字滤波器18），其根据延迟指数偏移第一数字基带信号S1和第二数字基带信号S2之一的相位，以便减小相位差。

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