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1. 发明授权

US08135103B1 Mixed domain spread spectrum clocking for use in imaging systems for maximum imaging quality and optimized EMI performance 有权
标题翻译：混合域扩频时钟，用于成像系统，实现最高的成像质量和优化的EMI性能
公开(公告)号：US08135103B1
公开(公告)日：2012-03-13
申请号：US12099666
申请日：2008-04-08
申请人： Matthew Courcy , David Barkin , James Brinkhurst
发明人： Matthew Courcy , David Barkin , James Brinkhurst
IPC分类号： H04L7/00 , H03D3/24 , H03L7/06
CPC分类号： H03L7/197
摘要： A method of operating a line imaging device including receiving a first clock signal indicative of a system timing signal in the line imaging device, generating a second clock signal based on the first clock signal and being unmodulated where the second clock signal being used for driving the imager timing, data sampling and digitizing operations of the line imaging device, and generating a third clock signal based on the first clock signal and being modulated using a spreading waveform where the third clock signal being a spread spectrum clock signal and being used to drive the data transfer operation of the line imaging device.
摘要翻译：一种操作线成像装置的方法，包括：接收在线成像装置中指示系统定时信号的第一时钟信号，基于第一时钟信号产生第二时钟信号，并且在第二时钟信号被用于驱动线性成像装置的成像器定时，数据采样和数字化操作，以及基于第一时钟信号产生第三时钟信号，并使用扩展波形进行调制，其中第三时钟信号是扩频时钟信号，并用于驱动线路成像设备的数据传输操作。

2. 发明授权

US07728753B2 Continuous synchronization for multiple ADCs 有权
标题翻译：连续同步多个ADC
公开(公告)号：US07728753B2
公开(公告)日：2010-06-01
申请号：US12250437
申请日：2008-10-13
申请人： Robert Callaghan Taft , Heinz Werker , Pier Francese , David Barkin
发明人： Robert Callaghan Taft , Heinz Werker , Pier Francese , David Barkin
IPC分类号： H03M1/34
CPC分类号： H03M1/0624 , H03M1/123 , H03M1/1245
摘要： A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.
摘要翻译：描述了用于多个ADC电路的连续同步的系统，装置和方法。 ADC电路可以被布置在系统内的主从配置中，使得转换器时钟被细分为数据输出时钟的较慢速度或用于控制将输出解复用到更宽的总线上，同时保持ADC到 -ADC同步对噪声和其他扰乱源的扰动具有弹性。主从配置中的ADC的配置可以根据顺序配置，并行配置或树型配置中的任何一个的总体系统要求以及其他配置而变化。可以对每个ADC电路进行数字和/或模拟定时调整。主时钟信号可以由主时钟发生器电路产生，该主时钟发生器电路在内部实现在ADC电路中，或外部实现为单独的主时钟发生器电路。

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