专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08276014B2 Stalling synchronisation circuits in response to a late data signal 有权
标题翻译：响应于后期数据信号的失速同步电路
公开(公告)号：US08276014B2
公开(公告)日：2012-09-25
申请号：US12656708
申请日：2010-02-12
申请人： Matthew Rudolph Fojtik , Dennis Michael Sylvester , David Theodore Blaauw , David Alan Fick
发明人： Matthew Rudolph Fojtik , Dennis Michael Sylvester , David Theodore Blaauw , David Alan Fick
IPC分类号： G06F1/12
CPC分类号： G06F11/0793 , G06F9/3869 , G06F11/0721
摘要： A data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a plurality of synchronization circuits for capturing and transmitting the data in response to a clock signal and a plurality of combinational circuits arranged between the synchronization circuits for processing the data, the plurality of synchronization circuits being arranged in at least two groups; an error detecting circuit for determining if the data input to one of the plurality of synchronization circuits is stable during a predetermined time and for signalling an error if the data input is unstable, the predetermined time being less than a half cycle of the clock signal; control circuitry responsive to said error detecting circuit signalling said error to transmit a control signal to at least one of said groups of synchronization circuits that contains a subsequent synchronization circuit that said synchronization circuit with said unstable input is configured to transmit said data to; each of said group of synchronization circuits being configured to respond to receipt of said control signal to stall for a clock cycle and to transmit a stall signal to at least one further group of synchronization circuits that said group of synchronization circuits is configured to transmit data to or receive data from; each of said group of synchronization circuits being configured to respond to receipt of said stall signal provided they have not stalled in a preceding clock cycle to stall for a clock cycle and to transmit a stall signal to said at least one further group of synchronization circuits.
摘要翻译：公开了一种用于处理数据的数据处理电路。数据处理电路包括：多个同步电路，用于响应于时钟信号捕获和发送数据;以及多个组合电路，布置在用于处理数据的同步电路之间，多个同步电路被布置在至少两个团体一个误差检测电路，用于确定输入到多个同步电路之一的数据在预定时间内是否稳定，如果数据输入不稳定则用于发信号通知，该预定时间小于该时钟信号的一半周期; 响应于所述错误检测电路的控制电路发信号通知所述错误，以将控制信号发送到所述同步电路组中的至少一个，该同步电路组包含随后的同步电路，所述同步电路与所述不稳定输入被配置为传送所述数据; 所述同步电路组中的每一个被配置为响应所述控制信号的接收以停止一个时钟周期，并且将失速信号发送到至少一组另一组同步电路，所述同步电路组被配置为将数据传输到或接收数据; 所述组同步电路中的每一个被配置为响应于所述失速信号的接收，只要它们在前一时钟周期内没有停止以停止时钟周期，并且将失速信号发送到所述至少另一组同步电路。

2. 发明申请

US20150015305A1 DYNAMIC CIRCUITRY USING PULSE AMPLIFICATION TO REDUCE METASTABILITY 有权
标题翻译：使用脉冲放大的动态电路降低均匀性
公开(公告)号：US20150015305A1
公开(公告)日：2015-01-15
申请号：US13940864
申请日：2013-07-12
申请人： Bharan GIRIDHAR , Matthew Rudolph Fojtik , David Alan Fick , Dennis Michael Sylvester , David Theodore Blaauw
发明人： Bharan GIRIDHAR , Matthew Rudolph Fojtik , David Alan Fick , Dennis Michael Sylvester , David Theodore Blaauw
IPC分类号： H03K19/003
CPC分类号： H03K3/0375 , H03K5/133 , H03K5/135
摘要： Synchronisation circuitry 2 comprises a first dynamic circuit stage 4 generating a first stage state signal which is pulse amplified by pulse amplifying circuitry 8 to generate a pulse amplified signal. The pulse amplified signal is supplied to a second dynamic circuit stage 6 where it is used to control generation of a second stage state signal. The pulse amplifying circuitry 8 comprises a chain of serially connected skewed inverters 20, 22. The action of the pulse amplifying circuitry 8 is to reduce the probability of metastability in the output of the second dynamic stage 6.
摘要翻译：同步电路2包括产生由脉冲放大电路8脉冲放大以产生脉冲放大信号的第一级状态信号的第一动态电路级4。脉冲放大信号被提供给第二动态电路级6，其中它用于控制第二级状态信号的产生。脉冲放大电路8包括串联连接的偏斜反相器20,22。脉冲放大电路8的作用是降低第二动态级6的输出中的亚稳态概率。

3. 发明申请

US20110202786A1 Stalling synchronisation circuits in response to a late data signal 有权
标题翻译：响应于后期数据信号的失速同步电路
公开(公告)号：US20110202786A1
公开(公告)日：2011-08-18
申请号：US12656708
申请日：2010-02-12
申请人： Matthew Rudolph Fojtik , Dennis Michael Sylvester , David Theodore Blaauw , David Alan Fick
发明人： Matthew Rudolph Fojtik , Dennis Michael Sylvester , David Theodore Blaauw , David Alan Fick
IPC分类号： G06F1/12
CPC分类号： G06F11/0793 , G06F9/3869 , G06F11/0721
摘要： A data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a plurality of synchronisation circuits for capturing and transmitting the data in response to a clock signal and a plurality of combinational circuits arranged between the synchronisation circuits for processing the data, the plurality of synchronisation circuits being arranged in at least two groups; an error detecting circuit for determining if the data input to one of the plurality of synchronisation circuits is stable during a predetermined time and for signalling an error if the data input is not stable, the predetermined time being less than a half cycle of the clock signal; control circuitry responsive to said error detecting circuit signalling said error to transmit a control signal to at least one of said groups of synchronisation circuits that contains a subsequent synchronisation circuit that said synchronisation circuit with said unstable input is configured to transmit said data to; each of said group of synchronisation circuits being configured to respond to receipt of said control signal to stall for a clock cycle and to transmit a stall signal to at least one further group of synchronisation circuits that said group of synchronisation circuits is configured to transmit data to or receive data from; each of said group of synchronisation circuits being configured to respond to receipt of said stall signal provided they have not stalled in a preceding clock cycle to stall for a clock cycle and to transmit a stall signal to said at least one further group of synchronisation circuits.
摘要翻译：公开了一种用于处理数据的数据处理电路。数据处理电路包括：多个同步电路，用于响应于时钟信号捕获和发送数据;以及多个组合电路，布置在用于处理数据的同步电路之间，多个同步电路被布置在至少两个团体一个误差检测电路，用于确定输入到多个同步电路之一的数据在预定时间内是否稳定，以及如果数据输入不稳定则用于发信号通知，该预定时间小于时钟信号的半个周期 ; 响应于所述错误检测电路的控制电路发信号通知所述错误，以将控制信号发送到所述同步电路组中的至少一个，该同步电路组包含随后的同步电路，所述同步电路与所述不稳定输入被配置为传送所述数据; 所述同步电路组中的每一个被配置为响应所述控制信号的接收以停止一个时钟周期，并且将失速信号发送到至少一组另一组同步电路，所述同步电路组被配置为将数据传输到或接收数据; 所述组同步电路中的每一个被配置为响应于所述失速信号的接收，只要它们在前一时钟周期内没有停止以停止时钟周期，并且将失速信号发送到所述至少另一组同步电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式