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1. 发明授权

US10050614B2 Method and system for reliable bootstrapping switches 有权
公开(公告)号：US10050614B2
公开(公告)日：2018-08-14
申请号：US15793581
申请日：2017-10-25
申请人： Maxlinear, Inc.
发明人： Yongjian Tang , Xuefeng Chen
IPC分类号： H03K17/16 , H03K17/06
摘要： Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.

2. 发明授权

US09929740B2 Successive-approximation register (SAR) analog-to-digital converter (ADC) with ultra low burst error rate 有权
公开(公告)号：US09929740B2
公开(公告)日：2018-03-27
申请号：US15478397
申请日：2017-04-04
申请人： MaxLinear, Inc.
发明人： Yongjian Tang
IPC分类号： H03M1/38 , H03M1/46 , H03M1/12 , H03M1/00 , H03M1/06
CPC分类号： H03M1/466 , H03M1/00 , H03M1/0695 , H03M1/12 , H03M1/125
摘要： Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment.

3. 发明授权

US09197239B2 Method and system for analog-to-digital converter with near-constant common mode voltage 有权
标题翻译：具有近常数共模电压的模数转换器的方法和系统
公开(公告)号：US09197239B2
公开(公告)日：2015-11-24
申请号：US14592020
申请日：2015-01-08
申请人： Maxlinear, Inc.
发明人： Yongjian Tang , Hao Liu
IPC分类号： H03M1/12 , H03M1/44
CPC分类号： H03M1/0609 , H03M1/0607 , H03M1/0682 , H03M1/1245 , H03M1/442 , H03M1/468
摘要： Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each of two input lines to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2x where x ranges from 0 to m−1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than VADC—fs/128 +VADC—fs/256+VADC—fs/512+VADC—fs/1024 when m equals 4 and where VADC—fs is the full-scale voltage of the ADC.
摘要翻译：具有近常数共模电压的模数转换器的方法和系统可以包括在具有到ADC的两个输入线中的每一个上的采样开关的模数转换器（ADC）中，N个双面和每个输入线上的M个单面开关电容器：通过关闭采样开关来采样输入电压，打开采样开关并比较输入线路之间的电压电平，将双侧开关电容器在参考电压（Vref）和接地并迭代地切换接地和电压之间的单侧开关电容，其可以等于Vref / 2x，其中x的范围从0到m-1，而m是每个输入线的单侧开关电容的数量。当m等于4时，ADC的共模偏移可能小于VADC-fs / 128 + VADC-fs / 256 + VADC-fs / 512 + VADC-fs / 1024，其中VADC-fs是 ADC。

4. 发明授权

US10355686B2 Method and system for reliable bootstrapping switches 有权
公开(公告)号：US10355686B2
公开(公告)日：2019-07-16
申请号：US16057499
申请日：2018-08-07
申请人： Maxlinear, Inc.
发明人： Yongjian Tang , Xuefeng Chen
IPC分类号： H03K17/06 , H03K17/687
摘要： Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.

5. 发明申请

US20170272091A1 SUCCESSIVE-APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC) WITH ULTRA LOW BURST ERROR RATE 有权
公开(公告)号：US20170272091A1
公开(公告)日：2017-09-21
申请号：US15478397
申请日：2017-04-04
申请人： MaxLinear, Inc.
发明人： Yongjian Tang
IPC分类号： H03M1/46 , H03M1/12
CPC分类号： H03M1/466 , H03M1/00 , H03M1/0695 , H03M1/12 , H03M1/125
摘要： Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment.

6. 发明授权

US10432212B2 Successive-approximation register (SAR) analog-to-digital converter (ADC) with ultra low burst error rate 有权
公开(公告)号：US10432212B2
公开(公告)日：2019-10-01
申请号：US15935567
申请日：2018-03-26
申请人： MaxLinear, Inc.
发明人： Yongjian Tang
IPC分类号： H03M1/38 , H03M1/46 , H03M1/12 , H03M1/00 , H03M1/06
摘要： Systems and methods are provided for enhanced analog-to-digital conversions, particularly by allowing for an ultra-low burst error rate. Analog-to-digital conversion may be applied to an analog input via one or more conversion cycles; and performance related parameter corresponding to the analog-to-digital conversion may be assessed. A digital output corresponding to the analog input may be generated, with the generating being controlled based on the assessing of the performance related parameter. The controlling may include adjusting at least a portion of the digital output. The assessing may include determining, for at least one conversion cycle, whether a performance related condition, corresponding to the performance related parameter, occurs. The determination may be based on an outcome of a matching search performed for that conversion cycle. The determination that the performance related condition occurs may be made when the matching search fails to settle within a corresponding time period.

7. 发明授权

US10326463B2 Method and system for charge compensation for switched capacitor circuits 有权
公开(公告)号：US10326463B2
公开(公告)日：2019-06-18
申请号：US15395586
申请日：2016-12-30
申请人： Maxlinear, Inc.
发明人： Hao Liu , Yongjian Tang
IPC分类号： H03M1/06 , H03H19/00 , H03M1/12 , H03M1/66
摘要： Methods and systems for charge compensation for switched-capacitor circuits may comprise, in an electronics device comprising a first voltage source, a switched capacitor load, and a switched capacitor compensation circuit: switching a capacitor in the switched capacitor load from a first voltage to a second voltage; providing a charge to the switched capacitor load from the switched capacitor compensation circuit without requiring added charge from the first voltage source. A reference voltage may be generated utilizing the first voltage source. A replica reference voltage for the switched capacitor compensation circuit may be generated utilizing a second voltage source. The replica reference voltage may be equal to the reference voltage. The replica reference voltage may be equal to a supply voltage, VDD, for circuitry in the electronics device. Capacitors may couple outputs of the first and second voltage sources to ground.

8. 发明申请

US20180351543A1 Method and System For Reliable Bootstrapping Switches 审中-公开
公开(公告)号：US20180351543A1
公开(公告)日：2018-12-06
申请号：US16057499
申请日：2018-08-07
申请人： Maxlinear, Inc.
发明人： Yongjian Tang , Xuefeng Chen
IPC分类号： H03K17/06 , H03K17/687
CPC分类号： H03K17/063 , H03K17/687 , H03K2217/0054
摘要： Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.

9. 发明授权

US10009034B2 Method and system for an analog-to-digital converter with near-constant common mode voltage 有权
公开(公告)号：US10009034B2
公开(公告)日：2018-06-26
申请号：US15718476
申请日：2017-09-28
申请人： Maxlinear, Inc.
发明人： Yongjian Tang , Hao Liu
IPC分类号： H03M1/12 , H03M1/06 , H03M1/44 , H03M1/46
CPC分类号： H03M1/0609 , H03M1/0607 , H03M1/0682 , H03M1/1245 , H03M1/442 , H03M1/468
摘要： Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each of two input lines to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2x where x ranges from 0 to m−1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than VADC_fs/128+VADC_fs/256+VADC_fs/512+VADC_fs/1024 when m equals 4 and where VADC_fs is the full-scale voltage of the ADC.

10. 发明申请

US20180019760A1 Method And System For An Analog-To-Digital Converter With Near-Constant Common Mode Voltage 有权
公开(公告)号：US20180019760A1
公开(公告)日：2018-01-18
申请号：US15718476
申请日：2017-09-28
申请人： Maxlinear, Inc.
发明人： Yongjian Tang , Hao Liu
IPC分类号： H03M1/06 , H03M1/44 , H03M1/12 , H03M1/46
CPC分类号： H03M1/0609 , H03M1/0607 , H03M1/0682 , H03M1/1245 , H03M1/442 , H03M1/468
摘要： Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each of two input lines to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2x where x ranges from 0 to m−1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than VADC_fs/128+VADC_fs/256+VADC_fs/512+VADC_fs/1024 when m equals 4 and where VADC_fs is the full-scale voltage of the ADC.

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