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1. 发明申请

US20110147948A1 FORMING METHOD AND STRUCTURE OF POROUS LOW-K LAYER, INTERCONNECT PROCESS AND INTERCONNECT STRUCTURE 有权
标题翻译：多孔低K层的形成方法和结构，互连过程和互连结构
公开(公告)号：US20110147948A1
公开(公告)日：2011-06-23
申请号：US13038612
申请日：2011-03-02
申请人： Mei-Ling Chen , Kuo-Chih Lai , Su-Jen Sung , Chien-Chung Huang , Yu-Tsung Lai
发明人： Mei-Ling Chen , Kuo-Chih Lai , Su-Jen Sung , Chien-Chung Huang , Yu-Tsung Lai
IPC分类号： H01L23/48 , B32B7/02
CPC分类号： H01L21/31695 , H01L21/02164 , H01L21/02203 , H01L21/02271 , H01L21/02304 , H01L21/02362 , H01L21/7682 , H01L21/76835 , Y10T428/24992
摘要： A structure of a porous low-k layer is described, comprising a bottom portion and a body portion of the same atomic composition, wherein the body portion is located on the bottom portion, and the bottom portion has a density higher than the density of the body portion. An interconnect structure is also described, including the above porous low-k layer, and a conductive layer filling up a damascene opening in the porous low-k layer.
摘要翻译：描述了多孔低k层的结构，其包括具有相同原子组成的底部和主体部分，其中主体部分位于底部，并且底部部分的密度高于身体部位。还描述了包括上述多孔低k层的互连结构以及填充多孔低k层中的镶嵌开口的导电层。

2. 发明授权

US08350246B2 Structure of porous low-k layer and interconnect structure 有权
标题翻译：多孔低k层和互连结构的结构
公开(公告)号：US08350246B2
公开(公告)日：2013-01-08
申请号：US13038612
申请日：2011-03-02
申请人： Mei-Ling Chen , Kuo-Chih Lai , Su-Jen Sung , Chien-Chung Huang , Yu-Tsung Lai
发明人： Mei-Ling Chen , Kuo-Chih Lai , Su-Jen Sung , Chien-Chung Huang , Yu-Tsung Lai
IPC分类号： H01L33/16 , H01L21/443
CPC分类号： H01L21/31695 , H01L21/02164 , H01L21/02203 , H01L21/02271 , H01L21/02304 , H01L21/02362 , H01L21/7682 , H01L21/76835 , Y10T428/24992
摘要： A structure of a porous low-k layer is described, comprising a bottom portion and a body portion of the same atomic composition, wherein the body portion is located on the bottom portion, and the bottom portion has a density higher than the density of the body portion. An interconnect structure is also described, including the above porous low-k layer, and a conductive layer filling up a damascene opening in the porous low-k layer.
摘要翻译：描述了多孔低k层的结构，其包括具有相同原子组成的底部和主体部分，其中主体部分位于底部，并且底部部分的密度高于身体部位。还描述了包括上述多孔低k层的互连结构以及填充多孔低k层中的镶嵌开口的导电层。

3. 发明授权

US07947565B2 Forming method of porous low-k layer and interconnect process 有权
标题翻译：多孔低k层和互连工艺的形成方法
公开(公告)号：US07947565B2
公开(公告)日：2011-05-24
申请号：US11672307
申请日：2007-02-07
申请人： Mei-Ling Chen , Kuo-Chih Lai , Su-Jen Sung , Chien-Chung Huang , Yu-Tsung Lai
发明人： Mei-Ling Chen , Kuo-Chih Lai , Su-Jen Sung , Chien-Chung Huang , Yu-Tsung Lai
IPC分类号： H01L21/443 , H01L33/16
CPC分类号： H01L21/31695 , H01L21/02164 , H01L21/02203 , H01L21/02271 , H01L21/02304 , H01L21/02362 , H01L21/7682 , H01L21/76835 , Y10T428/24992
摘要： A method of forming a porous low-k layer is described. A CVD process is conducted to a substrate, wherein a framework precursor and a porogen precursor are supplied. In an end period of the supply of the framework precursor, the value of at least one deposition parameter negatively correlated with the density of the product of the CVD process is decreased.
摘要翻译：描述形成多孔低k层的方法。对基材进行CVD工艺，其中提供骨架前体和致孔剂前体。在框架前体的供给的结束期间，减少与CVD工艺的产物的密度负相关的至少一个沉积参数的值。

4. 发明申请

US20080188088A1 FORMING METHOD AND STRUCTURE OF POROUS LOW-K LAYER, INTERCONNECT PROCESS AND INTERCONNECT STRUCTURE 有权
标题翻译：多孔低K层的形成方法和结构，互连过程和互连结构
公开(公告)号：US20080188088A1
公开(公告)日：2008-08-07
申请号：US11672307
申请日：2007-02-07
申请人： Mei-Ling Chen , Kuo-Chih Lai , Su-Jen Sung , Chien-Chung Huang , Yu-Tsung Lai
发明人： Mei-Ling Chen , Kuo-Chih Lai , Su-Jen Sung , Chien-Chung Huang , Yu-Tsung Lai
IPC分类号： H01L21/31
CPC分类号： H01L21/31695 , H01L21/02164 , H01L21/02203 , H01L21/02271 , H01L21/02304 , H01L21/02362 , H01L21/7682 , H01L21/76835 , Y10T428/24992
摘要： A method of forming a porous low-k layer is described. A CVD process is conducted to a substrate, wherein a framework precursor and a porogen precursor are supplied. In an end period of the supply of the framework precursor, the value of at least one deposition parameter negatively correlated with the density of the product of the CVD process is decreased.
摘要翻译：描述形成多孔低k层的方法。对基材进行CVD工艺，其中提供骨架前体和致孔剂前体。在框架前体的供给的结束期间，减少与CVD工艺的产物的密度负相关的至少一个沉积参数的值。

5. 发明申请

US20090061201A1 ULTRA LOW DIELECTRIC CONSTANT (K) DIELECTRIC LAYER AND METHOD OF FABRICATING THE SAME 有权
标题翻译：超低介电常数（K）电介质层及其制造方法
公开(公告)号：US20090061201A1
公开(公告)日：2009-03-05
申请号：US11850466
申请日：2007-09-05
申请人： Mei-Ling Chen , Su-Jen Sung , Chien-Chung Huang
发明人： Mei-Ling Chen , Su-Jen Sung , Chien-Chung Huang
IPC分类号： C23C14/54 , B32B3/26
CPC分类号： C23C16/401 , C23C16/45557 , C23C16/46 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/31695 , Y10T428/249953
摘要： A fabrication method of an ultra low-k dielectric layer is provided. A deposition process is performed, under the control of a temperature varying program or a pressure varying program, by reacting a dielectric matrix to form porous low-k dielectric layers with a gradient density on a barrier layer over a substrate.
摘要翻译：提供了一种超低k电介质层的制造方法。在温度变化程序或压力变化程序的控制下，通过使介电基质反应以在衬底上的阻挡层上形成具有梯度密度的多孔低k电介质层来进行沉积工艺。

6. 发明授权

US08092861B2 Method of fabricating an ultra dielectric constant (K) dielectric layer 有权
标题翻译：制造超介电常数（K）介电层的方法
公开(公告)号：US08092861B2
公开(公告)日：2012-01-10
申请号：US11850466
申请日：2007-09-05
申请人： Mei-Ling Chen , Su-Jen Sung , Chien-Chung Huang
发明人： Mei-Ling Chen , Su-Jen Sung , Chien-Chung Huang
IPC分类号： C23C16/30
CPC分类号： C23C16/401 , C23C16/45557 , C23C16/46 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/31695 , Y10T428/249953
摘要： A fabrication method of an ultra low-k dielectric layer is provided. A deposition process is performed, under the control of a temperature varying program or a pressure varying program, by reacting a dielectric matrix to form porous low-k dielectric layers with a gradient density on a barrier layer over a substrate.
摘要翻译：提供了一种超低k电介质层的制造方法。在温度变化程序或压力变化程序的控制下，通过使介电基质反应以在衬底上的阻挡层上形成具有梯度密度的多孔低k电介质层来进行沉积工艺。

7. 发明授权

US08163607B2 Semiconductor device and method of making the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08163607B2
公开(公告)日：2012-04-24
申请号：US12769649
申请日：2010-04-29
申请人： Yi-Wei Chen , Nien-Ting Ho , Kuo-Chih Lai , Chien-Chung Huang
发明人： Yi-Wei Chen , Nien-Ting Ho , Kuo-Chih Lai , Chien-Chung Huang
IPC分类号： H01L21/8283
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/26513 , H01L21/2652 , H01L21/28518 , H01L21/823443 , H01L21/823835 , H01L29/6659 , H01L29/7833
摘要： In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at meddle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.
摘要翻译：在本发明的方法中，在自对准硅化物工艺中，在第二热处理之前，将掺杂剂注入位于从中间高度的NixSi层到其前面的区域中，或者在形成NixSi层之前位于从NiSi层的预定厚度的一半的深度到位于NiSi层的预定前方的深度的硅层的范围内。在第二热处理期间允许掺杂剂与NixSi层一起加热以形成Si / NiSi 2 / NiSi界面，其可以降低SBH并提高串联电阻以获得具有优异性能的半导体器件。

8. 发明申请

US20120181635A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20120181635A1
公开(公告)日：2012-07-19
申请号：US13424398
申请日：2012-03-20
申请人： Yi-Wei Chen , Nien-Ting Ho , Kuo-Chih Lai , Chien-Chung Huang
发明人： Yi-Wei Chen , Nien-Ting Ho , Kuo-Chih Lai , Chien-Chung Huang
IPC分类号： H01L29/78
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/26513 , H01L21/2652 , H01L21/28518 , H01L21/823443 , H01L21/823835 , H01L29/6659 , H01L29/7833
摘要： In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at meddle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.
摘要翻译：在本发明的方法中，在自对准硅化物工艺中，在第二热处理之前，将掺杂剂注入位于从中间高度的NixSi层到其前面的区域中，或者在形成NixSi层之前位于从NiSi层的预定厚度的一半的深度到位于NiSi层的预定前方的深度的硅层的范围内。在第二热处理期间允许掺杂剂与NixSi层一起加热以形成Si / NiSi 2 / NiSi界面，其可以降低SBH并提高串联电阻以获得具有优异性能的半导体器件。

9. 发明申请

US20130149820A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20130149820A1
公开(公告)日：2013-06-13
申请号：US13323763
申请日：2011-12-12
申请人： Chien-Chung Huang , Kuo-Chih Lai
发明人： Chien-Chung Huang , Kuo-Chih Lai
IPC分类号： H01L21/8238
CPC分类号： H01L29/6659 , H01L21/28518 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7833 , H01L29/7847 , H01L29/7848
摘要： A method for manufacturing a semiconductor device includes providing a substrate having a first transistor device and a second transistor device formed thereon; forming a patterned stress film covering the second transistor device and exposing the first transistor device on the substrate; performing a pre-amorphous implantation (PAI) process to form an amorphous layer respectively at two sides of the first transistor device, and removing the patterned stress film.
摘要翻译：一种半导体器件的制造方法，包括提供具有第一晶体管器件和形成在其上的第二晶体管器件的衬底; 形成覆盖所述第二晶体管器件并使所述第一晶体管器件暴露于所述衬底上的图案化应力膜; 执行预非晶注入（PAI）工艺以分别在第一晶体管器件的两侧形成非晶层，以及去除图案化的应力膜。

10. 发明授权

US08067281B1 Method of fabricating complementary metal-oxide-semiconductor (CMOS) Device 有权
标题翻译：互补金属氧化物半导体（CMOS）器件的制造方法
公开(公告)号：US08067281B1
公开(公告)日：2011-11-29
申请号：US12830371
申请日：2010-07-05
申请人： Yi-Wei Chen , Chien-Chung Huang , Nien-Ting Ho , Kuo-Chih Lai
发明人： Yi-Wei Chen , Chien-Chung Huang , Nien-Ting Ho , Kuo-Chih Lai
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/7848
摘要： A method of fabricating a CMOS device is provided. First, first and second gates, first and second offset spacers and first and second lightly-doped regions are respectively formed in first and second type metal-oxide-semiconductor regions. A mask layer is respectively formed on the first and second gates. Next, an epitaxial layer is formed in the substrate on two sides of the second gate. Next, first and second spacers, first and second doped regions are formed. Next, a portion of the first spacer is removed to expose a portion of a surface of the first lightly-doped region, thereby forming a first slimmed spacer. Next, a coating layer containing silicon is formed to cover the exposed first lightly-doped region, the first and second doped regions. Next, the mask layer is removed. Next, a metal silicide layer is formed on the first and second gates and the silicon layer.
摘要翻译：提供一种制造CMOS器件的方法。首先，第一和第二栅极分别在第一和第二类型金属氧化物半导体区域中形成第一和第二偏移间隔物以及第一和第二轻掺杂区域。掩模层分别形成在第一和第二栅极上。接下来，在第二栅极的两侧的基板中形成外延层。接下来，形成第一和第二间隔物，形成第一和第二掺杂区域。接下来，去除第一间隔物的一部分以暴露第一轻掺杂区域的表面的一部分，从而形成第一细长间隔物。接下来，形成包含硅的涂层以覆盖暴露的第一轻掺杂区域，第一和第二掺杂区域。接下来，去除掩模层。接下来，在第一和第二栅极和硅层上形成金属硅化物层。

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