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    • 1. 发明授权
    • Rectifier with vertical MOS structure
    • 整流器具有垂直MOS结构
    • US08664701B2
    • 2014-03-04
    • US13446327
    • 2012-04-13
    • Kuo-Liang ChaoMei-Ling ChenHung-Hsin Kuo
    • Kuo-Liang ChaoMei-Ling ChenHung-Hsin Kuo
    • H01L21/02H01L21/322
    • H01L29/66143H01L21/28017H01L21/3086H01L29/407H01L29/456H01L29/66136H01L29/7813H01L29/861
    • A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure.
    • 提供一种制造具有垂直MOS结构的整流器的方法。 第一沟槽结构和第一掩模层形成在半导体衬底的第一侧。 第二沟槽结构形成在半导体衬底的第二侧。 栅极氧化层,多晶硅结构和金属溅射层依次形成在第二沟槽结构上。 整流器还包括湿式氧化物层和多个掺杂区域。 在第一多沟槽结构的表面和半导体衬底中形成湿氧化物层。 掺杂区形成在半导体衬底和第二沟槽结构之间的区域上,并且位于掩模层旁边。 金属溅射层形成在对应于第一沟槽结构的第一掩模层上。
    • 6. 发明授权
    • Enabling special modes within a digital device
    • 在数字设备中启用特殊模式
    • US07603601B2
    • 2009-10-13
    • US11355619
    • 2006-02-16
    • Cristian P. MasgrasMichael PyskaEdward Brian BolesJoseph W. TrieceIgor WojewodaMei-Ling Chen
    • Cristian P. MasgrasMichael PyskaEdward Brian BolesJoseph W. TrieceIgor WojewodaMei-Ling Chen
    • G01R31/3185
    • G01R31/31701G06F11/273G11C29/003G11C29/46
    • A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.
    • 特殊模式键匹配比较模块具有N存储元件和特殊模式键匹配比较器。 N存储元件累积串行数据流,然后确定数字设备是否应该以普通用户模式,公共编程模式或特定专用测试模式中操作。 为了减少意外解码错误测试或编程模式的可能性,数据流具有足够大数量的N位,以显着降低错误解码的概率。 为了进一步降低意外解码编程或测试模式的可能性,如果在N位串行数据流的累积期间检测到少于或多于N个时钟,则可以复位特殊模式键匹配比较模块。 特殊模式键匹配数据模式可以表示正常的用户模式,公共编程模式和特定的私人制造商测试模式。
    • 10. 发明申请
    • Reference Clock Out Feature on a Digital Device Peripheral Function Pin
    • 数字设备上的参考时钟输出功能外设功能引脚
    • US20080074205A1
    • 2008-03-27
    • US11776636
    • 2007-07-12
    • Mei-Ling ChenIgor WojewodaGaurang Kavaiya
    • Mei-Ling ChenIgor WojewodaGaurang Kavaiya
    • H03B1/00
    • G06F1/08
    • An integrated circuit device comprising a configurable reference clock output to a peripheral function connection of the integrated circuit device provides a system clock or a frequency divided clock from the system clock as a clock source to a peripheral function on a peripheral function connection of the integrated circuit device. The clock function may be used to generate all necessary clocks for a plurality of integrated circuit devices and may be able to supply a system clock or frequency divided clock from the system clock, either from an external clock oscillator source or from an internally generated system clock, with the option of using a crystal for more accuracy and greater frequency stability. The external clock and/or internal clock may be made available for peripheral devices even when internal logic of the integrated circuit device may be in a standby/sleep mode.
    • 一种集成电路装置,包括对集成电路装置的外围功能连接的可配置参考时钟输出,从集成电路的外围功能连接的系统时钟或分频时钟提供系统时钟作为时钟源到外围功能, 设备。 时钟功能可用于为多个集成电路器件产生所有必需的时钟,并且可以能够从系统时钟提供系统时钟或分频时钟,或者从外部时钟振荡器源或内部生成的系统时钟 ,可选择使用晶体更高的精度和更高的频率稳定性。 即使集成电路设备的内部逻辑可能处于待机/睡眠模式,外部时钟和/或内部时钟也可用于外围设备。