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1. 发明授权

US08587128B2 Damascene structure 有权
标题翻译：大马士革结构
公开(公告)号：US08587128B2
公开(公告)日：2013-11-19
申请号：US13397833
申请日：2012-02-16
申请人： Yu-Ru Yang , Chien-Chung Huang
发明人： Yu-Ru Yang , Chien-Chung Huang
IPC分类号： H01L23/48
CPC分类号： H01L21/2855 , H01L21/76844 , H01L21/76846
摘要： A damascene structure includes a conductive layer, a first dielectric layer, a first barrier metal layer, a barrier layer, and a second barrier metal layer sequentially formed on the conductive layer. The first dielectric layer having a via therein. The barrier layer is comprised of a material different with that of the first barrier metal layer. A bottom of the barrier layer disposed on the via bottom is not punched through. The accomplished barrier layers will have lower resistivity on the via bottom in the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.
摘要翻译：镶嵌结构包括依次形成在导电层上的导电层，第一介电层，第一阻挡金属层，阻挡层和第二阻挡金属层。第一电介质层中具有通孔。阻挡层由与第一阻挡金属层不同的材料构成。设置在通孔底部上的阻挡层的底部不穿孔。完成的阻挡层在第一介电层中的通孔底部具有较低的电阻率，并且它们能够防止铜原子扩散到电介质层中。

2. 发明授权

US08507350B2 Fabricating method of semiconductor elements 有权
标题翻译：半导体元件的制造方法
公开(公告)号：US08507350B2
公开(公告)日：2013-08-13
申请号：US13238045
申请日：2011-09-21
申请人： Chien-Chung Huang , Nien-Ting Ho
发明人： Chien-Chung Huang , Nien-Ting Ho
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26513 , H01L21/28518 , H01L21/76814 , H01L21/823425 , H01L29/66628 , H01L29/66636
摘要： A fabricating method of a semiconductor element includes the following steps. First, a substrate is provided. A metal gate structure and source/drain electrodes are already formed on the substrate. An amorphization process is performed in the source/drain electrodes to form an amorphous portion. An interlayer dielectric layer is formed on surfaces of the source/drain electrodes and a through hole contact is formed within the interlayer dielectric layer. A silicidation process is performed with the through hole contact and the amorphous portion of the source/drain electrodes to form a metal silicide layer. The fabricating method is capable of finishing the formation of the metal silicide layer in the condition that diameters of the through hole contact is becoming smaller and smaller.
摘要翻译：半导体元件的制造方法包括以下步骤。首先，提供基板。金属栅极结构和源极/漏极已经形成在衬底上。在源/漏电极中进行非晶化处理以形成非晶部分。在源/漏电极的表面上形成层间电介质层，并且在层间电介质层内形成通孔接触。利用通孔接触和源极/漏极的非晶部分进行硅化处理以形成金属硅化物层。该制造方法能够在通孔接触的直径变得越来越小的条件下完成金属硅化物层的形成。

3. 发明授权

US08344465B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08344465B2
公开(公告)日：2013-01-01
申请号：US13424398
申请日：2012-03-20
申请人： Yi-Wei Chen , Nien-Ting Ho , Kuo-Chih Lai , Chien-Chung Huang
发明人： Yi-Wei Chen , Nien-Ting Ho , Kuo-Chih Lai , Chien-Chung Huang
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/26513 , H01L21/2652 , H01L21/28518 , H01L21/823443 , H01L21/823835 , H01L29/6659 , H01L29/7833
摘要： In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at middle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.
摘要翻译：在本发明的方法中，在自对准硅化物工艺中，在第二热处理之前，将掺杂剂注入位于从中间高度的NixSi层到其前面的区域中，或者在形成NixSi层之前位于从NiSi层的预定厚度的一半的深度到位于NiSi层的预定前方的深度的硅层的范围内。在第二热处理期间允许掺杂剂与NixSi层一起加热以形成Si / NiSi 2 / NiSi界面，其可以降低SBH并提高串联电阻以获得具有优异性能的半导体器件。

4. 发明申请

US20120088345A1 METHOD OF FORMING SILICIDE FOR CONTACT PLUGS 审中-公开
标题翻译：形成接触片硅氧烷的方法
公开(公告)号：US20120088345A1
公开(公告)日：2012-04-12
申请号：US12902149
申请日：2010-10-12
申请人： Yi-Wei Chen , Kuo-Chih Lai , Nien-Ting Ho , Chien-Chung Huang
发明人： Yi-Wei Chen , Kuo-Chih Lai , Nien-Ting Ho , Chien-Chung Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/28518 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： A method for forming silicide is provided. First, a substrate is provided. Second, a gate structure is formed on the substrate which includes a silicon layer, a gate dielectric layer and at least one spacer. Then, a pair of source and drain is formed in the substrate and adjacent to the gate structure. Later, an interlayer dielectric layer is formed to cover the gate structure, the source and the drain. Afterwards, the interlayer dielectric layer is selectively removed to expose the gate structure. Next, multiple contact holes are formed in the interlayer dielectric layer to expose part of the substrate. Afterwards, the exposed substrate is converted to form silicide.
摘要翻译：提供了一种形成硅化物的方法。首先，提供基板。其次，在包括硅层，栅极电介质层和至少一个间隔物的基板上形成栅极结构。然后，在衬底中形成一对源极和漏极，并且与栅极结构相邻。然后，形成层间电介质层以覆盖栅极结构，源极和漏极。然后，选择性地去除层间绝缘层以露出栅极结构。接下来，在层间电介质层中形成多个接触孔，露出基板的一部分。之后，将曝光的基底转变成硅化物。

5. 发明授权

US07983051B2 DRAM module with solid state disk 有权
标题翻译：具有固态硬盘的DRAM模块
公开(公告)号：US07983051B2
公开(公告)日：2011-07-19
申请号：US12100023
申请日：2008-04-09
申请人： Jiunn-Chung Lee , Chien-Chung Huang
发明人： Jiunn-Chung Lee , Chien-Chung Huang
IPC分类号： H05K1/00
CPC分类号： H05K1/181 , G11C5/00 , H05K2201/09254 , H05K2201/10159 , H05K2201/10189 , Y02P70/611
摘要： A dynamic radon access memory (DRAM) module includes a printed circuit board, a number of DRAM units, a number of flash memory units, a number connecting pins and an interface controller. The DRAM units and the flash memory units are distributed on the printed circuit board. The connecting pins are formed at an edge of the printed circuit board. The interface controller is electrically connected to the flash memory units and a portion of the connecting pins, wherein each of the interface controller provides at least one serial interface between the flash memory units and the portion of connecting pins thereby enabling data transmission through the portion of connecting pins in at least one serial mode. The flash memory units integrally constitute a flash disk drive in the DRAM module. Therefore, frequently installation and uninstallation of the flash memory drive can be avoided. A motherboard assembly including the aforementioned DRAM module can be developed.
摘要翻译：动态氡存取存储器（DRAM）模块包括印刷电路板，多个DRAM单元，多个闪存单元，数字连接引脚和接口控制器。 DRAM单元和闪存单元分布在印刷电路板上。连接销形成在印刷电路板的边缘。接口控制器电连接到闪存单元和连接引脚的一部分，其中每个接口控制器在闪存单元和连接引脚的部分之间提供至少一个串行接口，从而使数据可以通过在至少一个串行模式下连接引脚。闪存单元一体地构成DRAM模块中的闪存盘驱动器。因此，可以避免闪存驱动器的频繁安装和卸载。可以开发包括上述DRAM模块的主板组件。

6. 发明授权

US07947565B2 Forming method of porous low-k layer and interconnect process 有权
标题翻译：多孔低k层和互连工艺的形成方法
公开(公告)号：US07947565B2
公开(公告)日：2011-05-24
申请号：US11672307
申请日：2007-02-07
申请人： Mei-Ling Chen , Kuo-Chih Lai , Su-Jen Sung , Chien-Chung Huang , Yu-Tsung Lai
发明人： Mei-Ling Chen , Kuo-Chih Lai , Su-Jen Sung , Chien-Chung Huang , Yu-Tsung Lai
IPC分类号： H01L21/443 , H01L33/16
CPC分类号： H01L21/31695 , H01L21/02164 , H01L21/02203 , H01L21/02271 , H01L21/02304 , H01L21/02362 , H01L21/7682 , H01L21/76835 , Y10T428/24992
摘要： A method of forming a porous low-k layer is described. A CVD process is conducted to a substrate, wherein a framework precursor and a porogen precursor are supplied. In an end period of the supply of the framework precursor, the value of at least one deposition parameter negatively correlated with the density of the product of the CVD process is decreased.
摘要翻译：描述形成多孔低k层的方法。对基材进行CVD工艺，其中提供骨架前体和致孔剂前体。在框架前体的供给的结束期间，减少与CVD工艺的产物的密度负相关的至少一个沉积参数的值。

7. 发明申请

US20100304042A1 METHOD FOR FORMING SUPERHIGH STRESS LAYER 审中-公开
标题翻译：形成超高压应力层的方法
公开(公告)号：US20100304042A1
公开(公告)日：2010-12-02
申请号：US12475595
申请日：2009-05-31
申请人： Hsiu-Lien Liao , Teng-Chun Tsai , Jei-Ming Chen , Yu-Tuan Tsai , Chien-Chung Huang
发明人： Hsiu-Lien Liao , Teng-Chun Tsai , Jei-Ming Chen , Yu-Tuan Tsai , Chien-Chung Huang
IPC分类号： B05D3/14
CPC分类号： H01L21/3185 , C23C16/0218 , C23C16/345 , H01L21/0217 , H01L21/02274 , H01L21/02315
摘要： A method for forming super high stress layer is provided. First, a substrate is provided. Second, an ammonia-related pretreatment is performed on the substrate. The flow rate of ammonia is not less than s.c.c.m. and the high-frequency source power is set to be not less than 800 W. Later, the super high stress layer is formed on the substrate having undergone the ammonia-related pretreatment.
摘要翻译：提供了一种形成超高应力层的方法。首先，提供基板。其次，在基板上进行与氨相关的预处理。氨的流量不小于s.c.c.m。高频源功率设定为800W以上。然后，在经过氨相关预处理的基板上形成超高应力层。

8. 发明申请

US20100254148A1 Lamp holder structure having heat dissipation fins 审中-公开
标题翻译：灯架结构具有散热片
公开(公告)号：US20100254148A1
公开(公告)日：2010-10-07
申请号：US12461032
申请日：2009-07-30
申请人： Chien-Chung Huang , Yen-Wei Ho
发明人： Chien-Chung Huang , Yen-Wei Ho
IPC分类号： F21V29/00
CPC分类号： F21V29/75 , F21S4/28 , F21V15/013 , F21V21/30 , F21V27/02 , F21V29/76 , F21V31/005 , F21Y2101/00 , F21Y2103/10 , F21Y2115/10
摘要： A lamp holder structure having heat dissipation fins comprises a base having a recess with threaded holes for install a luminous lamp set and at least one power line-in for connecting a power line. A plurality of heat dissipation fins arranged in parallel is extended and integrated from a corresponding exterior of the recess and a plurality of heat dissipation diverging fins is extended and integrated from an extreme exterior of the heat dissipation fins. Symmetric protruding plates are connected to predetermined places of the exterior of the base to pivotally connect a positioning plate capable of adjusting angles. A light-transmissive plate further seals the base and symmetric side strips are used to respectively lock symmetric frame borders of the base to position the light-transmissive plate. The corresponding sides of the recess of the base have locking holes for locking symmetric side covers.
摘要翻译：具有散热翅片的灯座结构包括具有用于安装发光灯组的螺纹孔的凹部和用于连接电力线的至少一个电源线的基座。平行布置的多个散热片从凹槽的相应外部延伸并整合，并且多个散热发散翅片从散热翅片的极端外部延伸和集成。对称突出板连接到基座的外部的预定位置，以枢转地连接能够调节角度的定位板。透光板进一步密封基座，对称侧条用于分别锁定基座的对称框架边界以定位透光板。基座的凹部的相应侧面具有用于锁定对称侧盖的锁定孔。

9. 发明授权

US07647132B2 Method and system for problem case packaging 失效
标题翻译：问题包装的方法和系统
公开(公告)号：US07647132B2
公开(公告)日：2010-01-12
申请号：US10839426
申请日：2004-05-05
申请人： Wen-Chang Kuo , Chien-Chung Huang , Tien-Der Chiang , Yi-Lin Huang , Chun Yi Chen , Dan-Ru Wang
发明人： Wen-Chang Kuo , Chien-Chung Huang , Tien-Der Chiang , Yi-Lin Huang , Chun Yi Chen , Dan-Ru Wang
IPC分类号： G06F19/00
CPC分类号： G06Q10/08
摘要： A method of problem case packaging handling consists collecting manufacturing problem information from entities associated with fabrication of a semiconductor product; and distributing the manufacturing problem information into problem cases which are stored in a problem database, each problem case representing a respective manufacturing problem and being associated with manufacturing problem information related to that problem case.
摘要翻译：问题案例包装处理的方法包括从制造半导体产品的实体收集制造问题信息; 并且将制造问题信息分发到存储在问题数据库中的问题情况下，每个问题情况表示相应的制造问题并与制造与该问题情况有关的问题信息相关联。

10. 发明授权

US07645698B2 Method for forming barrier layer 有权
标题翻译：形成阻挡层的方法
公开(公告)号：US07645698B2
公开(公告)日：2010-01-12
申请号：US11646387
申请日：2006-12-28
申请人： Yu-Ru Yang , Chien-Chung Huang
发明人： Yu-Ru Yang , Chien-Chung Huang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/2855 , H01L21/76846 , H01L21/76862
摘要： A method for forming barrier layers comprises steps of providing a conductive layer, forming a first dielectric layer on the conductive layer, the first dielectric layer having a via therein, forming a first metal layer covering the first dielectric layer and the conductive layer, forming a layer of metallized materials on the first metal layer, removing the layer of metallized materials above the via bottom in the first dielectric layer, and leaving the layer of metallized materials remaining on a sidewall of the via in the first dielectric layer; and forming a second metal layer covering the layer of metallized materials. The accomplished barrier layers will have lower resistivity in the bottom via of the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.
摘要翻译：形成阻挡层的方法包括以下步骤：提供导电层，在导电层上形成第一介电层，第一介电层在其中具有通孔，形成覆盖第一介电层和导电层的第一金属层，形成在第一金属层上的金属化材料层，去除第一介电层中的通孔底部上方的金属化材料层，并将金属化材料层留在第一介电层中的通孔的侧壁上; 以及形成覆盖所述金属化材料层的第二金属层。完成的阻挡层在第一介电层的底部通孔中将具有较低的电阻率，并且它们能够防止铜原子扩散到电介质层中。

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