专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120204079A1 SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEVICES VIA A MAIN MEMORY SYSTEM 有权
标题翻译：通过主存储系统连接协处理器和输入/输出设备的系统和方法
公开(公告)号：US20120204079A1
公开(公告)日：2012-08-09
申请号：US13303048
申请日：2011-11-22
申请人： Michael L. Takefman , Maher Amer , Riccardo Badalone
发明人： Michael L. Takefman , Maher Amer , Riccardo Badalone
IPC分类号： H03M13/09 , G06F13/36
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F9/4406 , G06F11/1016 , G06F11/1076 , G06F12/0246 , G06F12/0607 , G06F13/20 , G06F13/404 , G06F13/4221 , G06F13/4234 , G06F13/4282 , G06F2212/1008 , G06F2212/1032 , G06F2212/7201 , G06F2212/7208 , H03M13/05 , H03M13/27 , H04L9/0662
摘要： A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
摘要翻译：公开了一种用于与协处理器或输入/输出设备进行接口的系统。根据一个实施例，系统包括计算机处理单元，存储器模块，连接计算机处理单元和存储器模块的存储器总线以及协处理单元或输入/输出设备，其中存储器总线还将协处理单元或输入/输出设备到计算机处理单元。

2. 发明授权

US08713379B2 System and method of interfacing co-processors and input/output devices via a main memory system 有权
标题翻译：通过主存储器系统连接协处理器和输入/输出设备的系统和方法
公开(公告)号：US08713379B2
公开(公告)日：2014-04-29
申请号：US13303048
申请日：2011-11-22
申请人： Michael L. Takefman , Maher Amer , Riccardo Badalone
发明人： Michael L. Takefman , Maher Amer , Riccardo Badalone
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F9/4406 , G06F11/1016 , G06F11/1076 , G06F12/0246 , G06F12/0607 , G06F13/20 , G06F13/404 , G06F13/4221 , G06F13/4234 , G06F13/4282 , G06F2212/1008 , G06F2212/1032 , G06F2212/7201 , G06F2212/7208 , H03M13/05 , H03M13/27 , H04L9/0662
摘要： A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
摘要翻译：公开了一种用于与协处理器或输入/输出设备进行接口的系统。根据一个实施例，系统包括计算机处理单元，存储器模块，连接计算机处理单元和存储器模块的存储器总线以及协处理单元或输入/输出设备，其中存储器总线还将协处理单元或输入/输出设备到计算机处理单元。

3. 发明授权

US08107357B2 Optimized FFT/IFFT module 有权
标题翻译：优化FFT / IFFT模块
公开(公告)号：US08107357B2
公开(公告)日：2012-01-31
申请号：US11964510
申请日：2007-12-26
申请人： Maher Amer
发明人： Maher Amer
IPC分类号： H04J11/00 , H04L27/00 , H04B7/204 , G06F17/14
CPC分类号： H04L27/265 , G06F17/142 , H04L27/263
摘要： We disclose an optimal hardware implementation of the FFT/IFFT operation that minimizes the number of clock cycles required to compute the FFT/IFFT while at the same time minimizing the number of complex multipliers needed. An input module combines a plurality of inputs after applying a multiplication factor to each of the inputs. At least one multiplicand generator generates multiplicands. At least two complex multiplier modules perform complex multiplications with at least one of the complex multiplier modules receiving an output from the input module. A map module receives outputs of the at least two complex multiplier modules, the map module selecting and applying a multiplication factor to each of the outputs received to generate multiple outputs. Finally, an accumulation module receives and performs an accumulation task on each of the multiple outputs of the map module thereby generating a corresponding number of multiple outputs.
摘要翻译：我们公开了FFT / IFFT操作的最佳硬件实现，其最小化计算FFT / IFFT所需的时钟周期数，同时最小化所需复杂乘法器的数量。输入模块在将乘法因子应用于每个输入之后组合多个输入。至少一个被乘数发生器产生被乘数。至少两个复数乘法器模块执行复数乘法，复数乘法器模块中的至少一个从输入模块接收输出。地图模块接收至少两个复数乘法器模块的输出，地图模块选择并将乘法因子应用于接收的每个输出以产生多个输出。最后，积累模块在地图模块的多个输出的每一个上接收并执行累积任务，从而生成相应数量的多个输出。

4. 发明申请

US20050058059A1 Optimized FFT/IFFT module 有权
公开(公告)号：US20050058059A1
公开(公告)日：2005-03-17
申请号：US10662063
申请日：2003-09-12
申请人： Maher Amer
发明人： Maher Amer
IPC分类号： G06F17/14 , H04J11/00 , H04L27/26
CPC分类号： H04L27/265 , G06F17/142 , H04L27/263
摘要： The present invention discloses an optimal hardware implementation of the FFT/IFFT operation that minimizes the number of clock cycles required to compute the FFT/IFFT while at the same time minimizing the number of complex multipliers needed. For performing an N-point FFT/IFFT operation in N clock cycles, the optimal hardware implementation consists of several modules. An input module receives a plurality of inputs in parallel and combines the inputs after applying a multiplication factor to each of the inputs. At least one multiplicand generator is used to provide multiplicands to the system. At least two complex multiplier modules for performing complex multiplications are required with at least one of the complex multiplier modules receiving an output from the input module. Each of the complex multiplier modules receives multiplicands from the at least one multiplicand generator. Furthermore, at least one of the complex multiplier modules receives an output of another complex multiplier module. A map module is provided for receiving outputs of the at least two complex multiplier modules, the map module selecting and applying a multiplication factor to each of the outputs received to generate multiple outputs. Finally, an accumulation module receives and performs an accumulation task on each of the multiple outputs of the map module thereby generating a corresponding number of multiple outputs. In a preferred embodiment, the N-point FFT/IFFT operation is performed in N clock cycles using ( N 32 + 1 ) complex multipliers. In a specific implementation, a system comprising 3 complex multipliers is used to compute a 64-point FFT/IFFT operation in 64 clock cycles. Advantageously, the total number of clock cycles required to complete the FFT/IFFT operation is minimized while at the same time minimizing the number of complex multipliers needed.

5. 发明授权

US6141289A Structure of random access memory formed of multibit cells 失效
标题翻译：由多位单元组成的随机存取存储器的结构
公开(公告)号：US6141289A
公开(公告)日：2000-10-31
申请号：US277828
申请日：1999-03-29
申请人： Maher Amer
发明人： Maher Amer
IPC分类号： G11C5/06 , G11C8/16 , G11C11/56
CPC分类号： G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C5/06 , G11C8/16
摘要： The invention is an integrated circuit data storage array with storage cells disposed in an array of rows and columns with each cell having a number of subcells. The physical location of the subcells substantially reduces the space taken by horizontal data line used for accessing columns. This is accomplished by locating subcells of the same row number, the same bit number, and different column number adjacent to each other in the horizontal direction. As a result, a horizontal data line only extends between adjacent subcells and significantly reduces the wasted layout of multibit horizontal data lines.
摘要翻译：本发明是一种集成电路数据存储阵列，其存储单元设置成行和列的阵列，每个单元具有多个子单元。子单元的物理位置大大减少了用于访问列的水平数据线所占用的空间。这通过在水平方向上相邻的相同行号，相同位数和不同列号的子单元进行定位来实现。因此，水平数据线仅在相邻子单元之间延伸，并且显着地减少了多位水平数据线的浪费布局。

6. 发明授权

US07623585B2 Systems and modules for use with trellis-based decoding 失效
标题翻译：用于基于网格解码的系统和模块
公开(公告)号：US07623585B2
公开(公告)日：2009-11-24
申请号：US10377859
申请日：2003-02-28
申请人： Maher Amer
发明人： Maher Amer
IPC分类号： H04L27/28
CPC分类号： H03M13/6505 , H03M13/23 , H03M13/395 , H03M13/41 , H03M13/4169
摘要： Systems and modules for use in trellis-based decoding of convolutionally encoded sets of data bits. A first calculation module receives an encoded set of data bits and calculates a signal distance or a measure of the differences between the encoded set and each one of a group of predetermined states. The first calculation module consists of multiple parallel calculation submodules with each submodule being tasked to perform an XOR operation between the encoded set and one of the predetermined states. Multiple parallel second calculation modules each receiving the output of the first calculation module, calculate cumulative signal distances using the output of the first calculation module. Each second calculation module outputs its lowest valued cumulative signal distance and this may be used as input to a memory system for storing a database used in further decoding of the encoded data.
摘要翻译：用于卷积编码数据位集的网格解码中的系统和模块。第一计算模块接收编码的数据位集合，并计算编码集与一组预定状态中的每一组之间的差的信号距离或度量。第一个计算模块由多个并行计算子模块组成，每个子模块的任务是在编码集合和预定状态之一之间执行异或运算。多个并行第二计算模块，每个接收第一计算模块的输出，使用第一计算模块的输出计算累积信号距离。每个第二计算模块输出其最低值的累积信号距离，并且这可以用作存储系统的输入，用于存储在编码数据的进一步解码中使用的数据库。

7. 发明授权

US07333422B2 Optimized FFT/IFFT module 有权
公开(公告)号：US07333422B2
公开(公告)日：2008-02-19
申请号：US10662063
申请日：2003-09-12
申请人： Maher Amer
发明人： Maher Amer
IPC分类号： H04J11/00 , H04L27/06 , H04B7/204
CPC分类号： H04L27/265 , G06F17/142 , H04L27/263
摘要： The present invention discloses an optimal hardware implementation of the FFT/IFFT operation that minimizes the number of clock cycles required to compute the FFT/IFFT while at the same time minimizing the number of complex multipliers needed. For performing an N-point FFT/IFFT operation in N clock cycles, the optimal hardware implementation consists of several modules. An input module receives a plurality of inputs in parallel and combines the inputs after applying a multiplication factor to each of the inputs. At least one multiplicand generator is used to provide multiplicands to the system. At least two complex multiplier modules for performing complex multiplications are required with at least one of the complex multiplier modules receiving an output from the input module. Each of the complex multiplier modules receives multiplicands from the at least one multiplicand generator. Furthermore, at least one of the complex multiplier modules receives an output of another complex multiplier module. A map module is provided for receiving outputs of the at least two complex multiplier modules, the map module selecting and applying a multiplication factor to each of the outputs received to generate multiple outputs. Finally, an accumulation module receives and performs an accumulation task on each of the multiple outputs of the map module thereby generating a corresponding number of multiple outputs. In a preferred embodiment, the N-point FFT/IFFT operation is performed in N clock cycles using ( N 32 + 1 ) complex multipliers. In a specific implementation, a system comprising 3 complex multipliers is used to compute a 64-point FFT/IFFT operation in 64 clock cycles. Advantageously, the total number of clock cycles required to complete the FFT/IFFT operation is minimized while at the same time minimizing the number of complex multipliers needed.

8. 发明申请

US20100070690A1 LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR PROGRAMMING THE SAME 有权
标题翻译：负载减少双线内存模块（LRDIMM）及其编程方法
公开(公告)号：US20100070690A1
公开(公告)日：2010-03-18
申请号：US12559185
申请日：2009-09-14
申请人： Maher Amer , Michael Lewis Takefman
发明人： Maher Amer , Michael Lewis Takefman
IPC分类号： G06F12/00 , G06F15/177 , G06F12/02
CPC分类号： G06F3/0661 , G06F3/0611 , G06F3/0673 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C8/18 , G11C11/4093
摘要： A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual in-line memory module (RDIMM) in which control signals are synchronously buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM.
摘要翻译：减载双列直插存储器模块（LRDIMM）类似于注册的双列直插存储器模块（RDIMM），其中控制信号被同步缓冲，但LRDIMM也包括数据路径中的减载缓冲器（LRB）。为了使LRDIMM与系统存储器总线上的RDIMM兼容，LRDIMM的串行存在检测器（SPD）被编程具有修改的延迟支持和最小延迟值。当主机根据SPD提供的参数随后由主机设置LRDIMM的动态只读存储器（DRAM）设备时，所选择的等待时间值在增强的寄存器相位环（RPLL）中即时修改，设备。这具有补偿由LRB引入的延迟而不违反DRAM约束的作用，并为LRDIMM提供与RDIMM不兼容的存储器总线时序。

9. 发明授权

US07415112B2 Parallel scrambler/descrambler 失效
标题翻译：并行扰码器/解扰器
公开(公告)号：US07415112B2
公开(公告)日：2008-08-19
申请号：US10629640
申请日：2003-07-29
申请人： Maher Amer
发明人： Maher Amer
IPC分类号： H04L9/20
CPC分类号： H04L25/03872
摘要： Systems, methods and devices for scrambling/descrambling sets of data bits using subsets of a recurring sequence of scrambler bits. A self-synchronous scrambler, regardless of the generating polynomial being implemented, will generate repeating sequences of scrambler bits regardless of the initial stage of the scrambler. To implement a parallel scrambler, given a current state of the scrambler, the next n states of the scrambler are predicted based on the current state of the scrambler. The scrambling operation can then be preformed using the values in the current state—parallel logic operations between preselected bits of the current state will yield the required values to be used in scrambling an incoming parallel data set. Once these required values are generated, a parallel logical operation between the required values and the incoming data set will result in the scrambled output data. The current state of the scrambler is then incremented by n+1 by performing a predetermined set of logical operations between the various bits of the current state such that each bit of the n+1 state is a result of a logical operation between selected and predetermined bits of the current state.
摘要翻译：用于使用扰频器位的重复序列的子集对数据位进行加扰/解扰组的系统，方法和装置。无论生成多项式如何，自同步扰频器将产生扰频器比特的重复序列，而不管加扰器的初始阶段如何。为了实现并行扰频器，给定加扰器的当前状态，基于加扰器的当前状态预测扰频器的下一个n个状态。然后可以使用当前状态并行逻辑操作中的值来执行加扰操作，当前状态的预选位之间将产生要用于加扰输入并行数据集的所需值。一旦生成了这些所需的值，则所需值和输入数据组之间的并行逻辑运算将导致加扰的输出数据。然后，加扰器的当前状态通过执行当前状态的各个比特之间的预定的一组逻辑运算来增加n + 1 + 1，使得n + 1 / SUB>状态是当前状态的选定位和预定位之间的逻辑运算的结果。

10. 发明授权

US06728744B2 Wide word multiplier using booth encoding 有权
标题翻译：宽字倍增器使用展位编码
公开(公告)号：US06728744B2
公开(公告)日：2004-04-27
申请号：US09751399
申请日：2001-01-02
申请人： Maher Amer
发明人： Maher Amer
IPC分类号： G06F752
CPC分类号： G06F7/5324 , G06F7/5332
摘要： A multiplier for computing a final product of a first operand and a second operand comprising a multiplier array for forming a product of the first operand and second operand in carry-save form; a carry-save adder for adding said carry-save partial products and an accumulatd sum to produce a carry and save values; a carry-lookahead adder for adding said carry and save values to produce a product value and a carry-out value; a general purpose adder for adding said carry-out and said product value to produce said final product.
摘要翻译：一种用于计算第一操作数和第二操作数的最终乘积的乘法器，包括用于以进位保存形式形成第一操作数和第二操作数的乘积的乘法器阵列; 一个进位保存加法器，用于将所述进位保存部分乘积和积累和相加以产生进位和保存值; 用于将所述进位和保存值相加以产生乘积值和进位值的进位前瞻加法器; 用于将所述进位输出和所述乘积值相加以产生所述最终产品的通用加法器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式