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1. 发明授权

US07796652B2 Programmable asynchronous first-in-first-out (FIFO) structure with merging capability 有权
标题翻译：具有合并功能的可编程异步先进先出（FIFO）结构
公开(公告)号：US07796652B2
公开(公告)日：2010-09-14
申请号：US11790707
申请日：2007-04-27
申请人： Claus Reitlingshoefer , Dirk Pfaff , Riccardo Badalone
发明人： Claus Reitlingshoefer , Dirk Pfaff , Riccardo Badalone
IPC分类号： H04J3/04
CPC分类号： H04L7/033
摘要： Where high speed communication between a host and memory devices is carried over serial bit lanes, memory buffers are required for converting buffering the serial bit lanes, and for converting between serial and parallel formats. In addition, jitter, wander, and skew between the bit lanes need to be accommodated. The invention discloses a programmable asynchronous FIFO with the integrated ability to convert blocks of bits from serial to parallel as well as inserting bits from a parallel bus into the serial bit stream. The invention provides very low latency and can be implemented in low power technologies.
摘要翻译：在主机和存储器件之间的高速通信通过串行位通道传送的情况下，需要存储器缓冲器来转换缓冲串行位通道，以及用于串行和并行格式之间的转换。此外，需要适应位线之间的抖动，漂移和偏斜。本发明公开了一种具有集成能力的可编程异步FIFO，其将位块的串行转换为并行转换，并将位从并行总线插入串行位流。本发明提供非常低的延迟并且可以在低功率技术中实现。

2. 发明授权

US08315349B2 Bang-bang phase detector with sub-rate clock 有权
标题翻译： Bang-bang相位检测器带子速率时钟
公开(公告)号：US08315349B2
公开(公告)日：2012-11-20
申请号：US12258440
申请日：2008-10-26
申请人： Riccardo Badalone
发明人： Riccardo Badalone
IPC分类号： H03D3/24
CPC分类号： H03D13/004
摘要： The present invention describes methods and circuitry for a sub-rate bang-bang phase detector, in which the reference clock has frequency that is a fraction of the bit rate of the received data stream. The sub-rate bang-bang phase detector is enabled by multiple phases of the reference clock.
摘要翻译：本发明描述了用于子速率爆炸相位检测器的方法和电路，其中参考时钟的频率是接收数据流的比特率的一部分。子速率爆炸相位检测器由参考时钟的多个相位启用。

3. 发明授权

US07940839B2 Fully adaptive equalization for high loss communications channels 有权
标题翻译：高损耗通信信道的全自适应均衡
公开(公告)号：US07940839B2
公开(公告)日：2011-05-10
申请号：US10597455
申请日：2005-01-26
申请人： Marcel Lapointe , Albert Vareljian , Riccardo Badalone
发明人： Marcel Lapointe , Albert Vareljian , Riccardo Badalone
IPC分类号： H03K5/159 , H03H7/30
CPC分类号： H04B3/04 , H04L25/0307 , H04L25/03159 , H04L25/03343 , H04L25/03885 , H04L2025/03356 , H04L2025/03636
摘要： An equalization circuit is disclosed that enables high data rate transmission over high loss communications channels. Also disclosed is a set of functional blocks and update criteria that allow for the equalization function to be adapted for a large variety of different communications channels. A fully continuous adaptive equalizer is used in conjunction with a Decision Feedback Equalizer to fully equalize a large number of communications channels.
摘要翻译：公开了一种能够通过高损耗通信信道实现高数据速率传输的均衡电路。还公开了一组功能块和更新标准，其允许均衡功能适用于各种不同的通信信道。完全连续的自适应均衡器与判决反馈均衡器结合使用，以完全均衡大量通信信道。

4. 发明授权

US08713379B2 System and method of interfacing co-processors and input/output devices via a main memory system 有权
标题翻译：通过主存储器系统连接协处理器和输入/输出设备的系统和方法
公开(公告)号：US08713379B2
公开(公告)日：2014-04-29
申请号：US13303048
申请日：2011-11-22
申请人： Michael L. Takefman , Maher Amer , Riccardo Badalone
发明人： Michael L. Takefman , Maher Amer , Riccardo Badalone
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F9/4406 , G06F11/1016 , G06F11/1076 , G06F12/0246 , G06F12/0607 , G06F13/20 , G06F13/404 , G06F13/4221 , G06F13/4234 , G06F13/4282 , G06F2212/1008 , G06F2212/1032 , G06F2212/7201 , G06F2212/7208 , H03M13/05 , H03M13/27 , H04L9/0662
摘要： A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
摘要翻译：公开了一种用于与协处理器或输入/输出设备进行接口的系统。根据一个实施例，系统包括计算机处理单元，存储器模块，连接计算机处理单元和存储器模块的存储器总线以及协处理单元或输入/输出设备，其中存储器总线还将协处理单元或输入/输出设备到计算机处理单元。

5. 发明申请

US20080260016A1 Fully Adaptive Equalization for High Loss Communications Channels 有权
标题翻译：高损耗通信信道的全自适应均衡
公开(公告)号：US20080260016A1
公开(公告)日：2008-10-23
申请号：US10597455
申请日：2005-01-26
申请人： Marcel Lapointe , Albert Vareljian , Riccardo Badalone
发明人： Marcel Lapointe , Albert Vareljian , Riccardo Badalone
IPC分类号： H04L27/01
CPC分类号： H04B3/04 , H04L25/0307 , H04L25/03159 , H04L25/03343 , H04L25/03885 , H04L2025/03356 , H04L2025/03636
摘要： An equalization circuit is disclosed that enables high data rate transmission over high loss communications channels. Also disclosed is a set of functional blocks and update criteria that allow for the equalization function to be adapted for a large variety of different communications channels. A fully continuous adaptive equalizer is used in conjunction with a Decision Feedback Equalizer to fully equalize a large number of communications channels.
摘要翻译：公开了一种能够通过高损耗通信信道实现高数据速率传输的均衡电路。还公开了一组功能块和更新标准，其允许均衡功能适用于各种不同的通信信道。完全连续的自适应均衡器与判决反馈均衡器结合使用，以完全均衡大量通信信道。

6. 发明申请

US20120204079A1 SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEVICES VIA A MAIN MEMORY SYSTEM 有权
标题翻译：通过主存储系统连接协处理器和输入/输出设备的系统和方法
公开(公告)号：US20120204079A1
公开(公告)日：2012-08-09
申请号：US13303048
申请日：2011-11-22
申请人： Michael L. Takefman , Maher Amer , Riccardo Badalone
发明人： Michael L. Takefman , Maher Amer , Riccardo Badalone
IPC分类号： H03M13/09 , G06F13/36
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F9/4406 , G06F11/1016 , G06F11/1076 , G06F12/0246 , G06F12/0607 , G06F13/20 , G06F13/404 , G06F13/4221 , G06F13/4234 , G06F13/4282 , G06F2212/1008 , G06F2212/1032 , G06F2212/7201 , G06F2212/7208 , H03M13/05 , H03M13/27 , H04L9/0662
摘要： A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
摘要翻译：公开了一种用于与协处理器或输入/输出设备进行接口的系统。根据一个实施例，系统包括计算机处理单元，存储器模块，连接计算机处理单元和存储器模块的存储器总线以及协处理单元或输入/输出设备，其中存储器总线还将协处理单元或输入/输出设备到计算机处理单元。

7. 发明申请

US20090110136A1 BANG-BANG PHASE DETECTOR WITH SUB-RATE CLOCK 有权
标题翻译：具有次级时钟的BANG-BANG相位检测器
公开(公告)号：US20090110136A1
公开(公告)日：2009-04-30
申请号：US12258440
申请日：2008-10-26
申请人： Riccardo BADALONE
发明人： Riccardo BADALONE
IPC分类号： H03D3/24
CPC分类号： H03D13/004
摘要： The present invention describes methods and circuitry for a sub-rate bang-bang phase detector, in which the reference clock has frequency that is a fraction of the bit rate of the received data stream. The sub-rate bang-bang phase detector is enabled by multiple phases of the reference clock.
摘要翻译：本发明描述了用于子速率爆炸相位检测器的方法和电路，其中参考时钟的频率是接收数据流的比特率的一部分。子速率爆炸相位检测器由参考时钟的多个相位启用。

8. 发明授权

US08081677B2 Receiver-based adaptive equalizer with pre-cursor compensation 有权
标题翻译：基于接收机的自适应均衡器具有前置补偿功能
公开(公告)号：US08081677B2
公开(公告)日：2011-12-20
申请号：US11720024
申请日：2005-11-22
申请人： Riccardo Badalone
发明人： Riccardo Badalone
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03617
摘要： An equalization circuit is disclosed that enables high data rate transmission over high loss communications channels. Also disclosed is a set of functional blocks and update criteria that allow for the equalization function to be adapted for a large variety of different communications channels. A fully continuous adaptive equalizer is used in conjunction with a Decision Feedback Equalizer to fully equalize a wide range of communications channels. Interoperability and Bit Error Rate performance are optimized through compensation of pre-cursor inter-symbol interference, which is performed adaptively in the receiver as opposed to the transmitter.
摘要翻译：公开了一种能够通过高损耗通信信道实现高数据速率传输的均衡电路。还公开了一组功能块和更新标准，其允许均衡功能适用于各种不同的通信信道。完全连续的自适应均衡器与决策反馈均衡器结合使用，以完全均衡各种通信信道。互操作性和误码率性能通过对接收机中自适应执行的前置符号间干扰的补偿进行优化，与发射机相反。

9. 发明申请

US20080240223A1 Receiver-Based Adaptive Equalizer with Pre-Cursor Compensation 有权
标题翻译：基于接收机的自适应均衡器，具有预光标补偿
公开(公告)号：US20080240223A1
公开(公告)日：2008-10-02
申请号：US11720024
申请日：2005-11-22
申请人： Riccardo Badalone
发明人： Riccardo Badalone
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03617
摘要： An equalization circuit is disclosed that enables high data rate transmission over high loss communications channels. Also disclosed is a set of functional blocks and update criteria that allow for the equalization function to be adapted for a large variety of different communications channels. A fully continuous adaptive equalizer is used in conjunction with a Decision Feedback Equalizer to fully equalize a wide range of communications channels. Interoperability and Bit Error Rate performance are optimized through compensation of pre-cursor inter-symbol interference, which is performed adaptively in the receiver as opposed to the transmitter.
摘要翻译：公开了一种能够通过高损耗通信信道实现高数据速率传输的均衡电路。还公开了一组功能块和更新标准，其允许均衡功能适用于各种不同的通信信道。完全连续的自适应均衡器与决策反馈均衡器结合使用，以完全均衡各种通信信道。互操作性和误码率性能通过对接收机中自适应执行的前置符号间干扰的补偿进行优化，与发射机相反。

10. 发明申请

US20070258491A1 Programmable asynchronous first-in-first-out (FIFO) structure with merging capability 有权
标题翻译：具有合并功能的可编程异步先进先出（FIFO）结构
公开(公告)号：US20070258491A1
公开(公告)日：2007-11-08
申请号：US11790707
申请日：2007-04-27
申请人： Claus Reitlingshoefer , Dirk Pfaff , Riccardo Badalone
发明人： Claus Reitlingshoefer , Dirk Pfaff , Riccardo Badalone
IPC分类号： H04J3/04
CPC分类号： H04L7/033
摘要： Where high speed communication between a host and memory devices is carried over serial bit lanes, memory buffers are required for converting buffering the serial bit lanes, and for converting between serial and parallel formats. In addition, jitter, wander, and skew between the bit lanes need to be accommodated. The invention discloses a programmable asynchronous FIFO with the integrated ability to convert blocks of bits from serial to parallel as well as inserting bits from a parallel bus into the serial bit stream. The invention provides very low latency and can be implemented in low power technologies.
摘要翻译：在主机和存储器件之间的高速通信通过串行位通道传送的情况下，需要存储器缓冲器来转换缓冲串行位通道，以及用于串行和并行格式之间的转换。此外，需要适应位线之间的抖动，漂移和偏斜。本发明公开了一种具有集成能力的可编程异步FIFO，其将位块的串行转换为并行转换，并将位从并行总线插入串行位流。本发明提供非常低的延迟并且可以在低功率技术中实现。

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