专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08010750B2 Network on chip that maintains cache coherency with invalidate commands 失效
标题翻译：使用无效命令维护高速缓存一致性的片上网络
公开(公告)号：US08010750B2
公开(公告)日：2011-08-30
申请号：US12015975
申请日：2008-01-17
申请人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich
发明人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich
IPC分类号： G06F12/00
CPC分类号： G06F12/0833
摘要： A network on chip (‘NOC’) including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, wherein the memory communications controller configured to execute a memory access instruction and configured to determine a state of a cache line addressed by the memory access instruction, the state of the cache line being one of shared, exclusive, or invalid; the memory communications controller configured to broadcast an invalidate command to a plurality of IP blocks of the NOC if the state of the cache line is shared; and the memory communications controller configured to transmit an invalidate command only to an IP block that controls a cache where the cache line is stored if the state of the cache line is exclusive.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），其中所述存储器通信控制器被配置为执行存储器访问指令并且被配置为确定由存储器访问指令寻址的高速缓存行，高速缓存行的状态是共享，排他或无效之一; 所述存储器通信控制器被配置为如果所述高速缓存行的状态被共享，则向所述NOC的多个IP块广播无效命令; 以及所述存储器通信控制器被配置为仅当所述高速缓存行的状态是排他性时，将无效命令仅发送到控制高速缓存行存储的高速缓存的IP块。

2. 发明授权

US07917703B2 Network on chip that maintains cache coherency with invalidate commands 失效
标题翻译：使用无效命令维护高速缓存一致性的片上网络
公开(公告)号：US07917703B2
公开(公告)日：2011-03-29
申请号：US11955553
申请日：2007-12-13
申请人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0837 , G06F15/7825
摘要： A network on chip (‘NOC’) comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block coupled to a router through a memory communications controller and a network interface controller, the NOC also including a port on a router of the network through which is received an invalidate command, the invalidate command including an identification of a cache line, the invalidate command representing an instruction to invalidate the cache line, the router configured to send the invalidate command to an IP block served by the router; the router further configured to send the invalidate command horizontally and vertically to neighboring routers if the port is a vertical port; and the router further configured to send the invalidate command only horizontally to neighboring routers if the port is a horizontal port.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器耦合到路由器，NOC 还包括在通过其接收到无效命令的网络的路由器上的端口，包括高速缓存行的标识的无效命令，表示使高速缓存行无效的指令的无效命令，被配置为将无效命令发送到由路由器服务的IP块; 路由器还配置为如果端口是垂直端口，则将无效命令水平和垂直地发送到相邻路由器; 并且该路由器还被配置为仅当该端口是水平端口时才将水平地发送到相邻路由器的invalidate命令。

3. 发明申请

US20090157976A1 Network on Chip That Maintains Cache Coherency With Invalidate Commands 失效
标题翻译：使用无效命令维护缓存一致性的片上网络
公开(公告)号：US20090157976A1
公开(公告)日：2009-06-18
申请号：US11955553
申请日：2007-12-13
申请人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0837 , G06F15/7825
摘要： A network on chip (‘NOC’) that maintains cache coherency with invalidate commands, the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, the NOC also including a port on a router of the network through which is received an invalidate command, the invalidate command including an identification of a cache line, the invalidate command representing an instruction to invalidate the cache line, the router configured to send the invalidate command to an IP block served by the router; the router further configured to send the invalidate command horizontally and vertically to neighboring routers if the port is a vertical port; and the router further configured to send the invalidate command only horizontally to neighboring routers if the port is a horizontal port.
摘要翻译：片上网络（“NOC”）通过无效命令维持高速缓存一致性，NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器适配于路由器通信控制器和网络接口控制器，NOC还包括接收到无效命令的网络的路由器上的端口，包括高速缓存行的标识的无效命令，表示使高速缓存行无效的指令的无效命令路由器被配置为将无效命令发送到由路由器服务的IP块; 路由器还配置为如果端口是垂直端口，则将无效命令水平和垂直地发送到相邻路由器; 并且该路由器还被配置为仅当该端口是水平端口时才将水平地发送到相邻路由器的invalidate命令。

4. 发明授权

US08392664B2 Network on chip 有权
标题翻译：网络芯片
公开(公告)号：US08392664B2
公开(公告)日：2013-03-05
申请号：US12118017
申请日：2008-05-09
申请人： Miguel Comparan , Russell D. Hoover , Eric O. Mejdrich
发明人： Miguel Comparan , Russell D. Hoover , Eric O. Mejdrich
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/126
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; and at least one IP block also including a computer processor and an L1, write-through data cache comprising high speed local memory on the IP block, the cache controlled by a cache controller having a cache line replacement policy, the cache controller configured to lock segments of the cache, the computer processor configured to store thread-private data in main memory off the IP block, the computer processor further configured to store thread-private data on a segment of the L1 data cache, the segment locked against replacement upon cache misses under the cache controller's replacement policy, the segment further locked against write-through to main memory.
摘要翻译：包括集成处理器（IP）块，路由器，存储器通信控制器和网络接口控制器的片上网络（NOC）每个IP块通过存储器通信控制器和网络接口控制器适应于路由器; 以及至少一个IP块，其还包括计算机处理器和包括IP块上的高速本地存储器的L1，直通数据高速缓存，由具有高速缓存行替换策略的高速缓存控制器控制的高速缓存，高速缓存控制器被配置为锁定所述计算机处理器被配置为将主存储器中的线程专用数据存储在所述IP块之外，所述计算机处理器还被配置为将线程专用数据存储在所述L1数据高速缓存的段上，所述段被锁定以防止在高速缓存错过了缓存控制器的替换策略，该段进一步锁定到主内存的写入。

5. 发明申请

US20090282197A1 Network On Chip 有权
标题翻译：网络芯片
公开(公告)号：US20090282197A1
公开(公告)日：2009-11-12
申请号：US12118017
申请日：2008-05-09
申请人： Miguel Comparan , Russell D. Hoover , Eric O. Mejdrich
发明人： Miguel Comparan , Russell D. Hoover , Eric O. Mejdrich
IPC分类号： G06F12/08
CPC分类号： G06F12/126
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; and at least one IP block also including a computer processor and an L1, write-through data cache comprising high speed local memory on the IP block, the cache controlled by a cache controller having a cache line replacement policy, the cache controller configured to lock segments of the cache, the computer processor configured to store thread-private data in main memory off the IP block, the computer processor further configured to store thread-private data on a segment of the L1 data cache, the segment locked against replacement upon cache misses under the cache controller's replacement policy, the segment further locked against write-through to main memory.
摘要翻译：片上网络（“NOC”）包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器; 每个IP块通过存储器通信控制器和网络接口控制器适应于路由器; 以及至少一个IP块，其还包括计算机处理器和包括IP块上的高速本地存储器的L1，直通数据高速缓存，由具有高速缓存行替换策略的高速缓存控制器控制的高速缓存，高速缓存控制器被配置为锁定所述计算机处理器被配置为将主存储器中的线程专用数据存储在所述IP块之外，所述计算机处理器还被配置为将线程专用数据存储在所述L1数据高速缓存的段上，所述段被锁定以防止在高速缓存错过了缓存控制器的替换策略，该段进一步锁定到主内存的写入。

6. 发明申请

US20090187716A1 Network On Chip that Maintains Cache Coherency with Invalidate Commands 失效
标题翻译：使用无效命令保持缓存一致性的片上网络
公开(公告)号：US20090187716A1
公开(公告)日：2009-07-23
申请号：US12015975
申请日：2008-01-17
申请人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich
发明人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich
IPC分类号： G06F12/08
CPC分类号： G06F12/0833
摘要： A network on chip (‘NOC’) that maintains cache coherency, the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, at least one memory communications controller further comprising a cache coherency controller each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, wherein the memory communications controller configured to execute a memory access instruction and configured to determine a state of a cache line addressed by the memory access instruction, the state of the cache line being one of shared, exclusive, or invalid; the memory communications controller configured to broadcast an invalidate command to a plurality of IP blocks of the NOC if the state of the cache line is shared; and the memory communications controller configured to transmit an invalidate command only to an IP block that controls a cache where the cache line is stored if the state of the cache line is exclusive.
摘要翻译：一种保持高速缓存一致性的网络芯片（NOC），NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器适应于路由器，网络接口控制器，至少一个存储器通信控制器，其还包括高速缓存一致性控制器，每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器，其中所述存储器通信控制器被配置执行存储器访问指令并被配置为确定由存储器访问指令寻址的高速缓存行的状态，高速缓存行的状态是共享的，排他的或无效的之一; 所述存储器通信控制器被配置为如果所述高速缓存行的状态被共享，则向所述NOC的多个IP块广播无效命令; 以及所述存储器通信控制器被配置为仅当所述高速缓存行的状态是排他性时，将无效命令仅发送到控制高速缓存行存储的高速缓存的IP块。

7. 发明授权

US08020168B2 Dynamic virtual software pipelining on a network on chip 失效
标题翻译：在芯片上的动态虚拟软件流水线
公开(公告)号：US08020168B2
公开(公告)日：2011-09-13
申请号：US12117897
申请日：2008-05-09
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F15/76 , G06F9/46
CPC分类号： G06F15/17356 , G06F15/7825
摘要： A NOC for dynamic virtual software pipelining including IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, the NOC also including: a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, each stage assigned to a thread of execution on an IP block; and each stage executing on a thread of execution on an IP block, including a first stage executing on an IP block, producing output data and sending by the first stage the produced output data to a second stage, the output data including control information for the next stage and payload data; and the second stage consuming the produced output data in dependence upon the control information.
摘要翻译：一种用于动态虚拟软件流水线的NOC，包括IP块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，NOC还包括：计算机软件应用程序分段每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段分配给IP块上的执行线程; 并且每个阶段在IP块上执行的执行线程，包括在IP块上执行的第一阶段，产生输出数据，并且通过第一阶段将产生的输出数据发送到第二阶段，所述输出数据包括用于下一阶段和有效载荷数据; 并且第二阶段根据控制信息消耗所产生的输出数据。

8. 发明申请

US20090282222A1 Dynamic Virtual Software Pipelining On A Network On Chip 失效
标题翻译：网络上的动态虚拟软件流水线
公开(公告)号：US20090282222A1
公开(公告)日：2009-11-12
申请号：US12117897
申请日：2008-05-09
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F9/30
CPC分类号： G06F15/17356 , G06F15/7825
摘要： A NOC for dynamic virtual software pipelining including IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, the NOC also including: a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, each stage assigned to a thread of execution on an IP block; and each stage executing on a thread of execution on an IP block, including a first stage executing on an IP block, producing output data and sending by the first stage the produced output data to a second stage, the output data including control information for the next stage and payload data; and the second stage consuming the produced output data in dependence upon the control information.
摘要翻译：一种用于动态虚拟软件流水线的NOC，包括IP块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，NOC还包括：计算机软件应用程序分段每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段分配给IP块上的执行线程; 并且每个阶段在IP块上执行的执行线程，包括在IP块上执行的第一阶段，产生输出数据，并且通过第一阶段将产生的输出数据发送到第二阶段，所述输出数据包括用于下一阶段和有效载荷数据; 并且第二阶段根据控制信息消耗所产生的输出数据。

9. 发明申请

US20090138567A1 Network on chip with partitions 失效
标题翻译：网络芯片与分区
公开(公告)号：US20090138567A1
公开(公告)日：2009-05-28
申请号：US12102038
申请日：2008-04-14
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F15/167
CPC分类号： G06F15/16
摘要： A design structure embodied in a machine readable medium is provided. Embodiments of the design structure include a network on chip (‘NOC’), the NOC comprising: integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers; the network organized into partitions, each partition including at least one IP block, each partition assigned exclusive access to a separate physical memory address space; and one or more applications executing on one or more of the partitions.
摘要翻译：提供体现在机器可读介质中的设计结构。该设计结构的实施例包括片上网络（NOC），NOC包括：集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器适配于路由器通信控制器和网络接口控制器，每个存储器通信控制器控制IP块和存储器之间的通信，以及每个网络接口控制器通过路由器控制IP间块通信; 网络组织成分区，每个分区包括至少一个IP块，每个分区分配独占访问单独的物理内存地址空间; 以及在一个或多个分区上执行的一个或多个应用程序。

10. 发明申请

US20090109996A1 Network on Chip 审中-公开
标题翻译：网络芯片
公开(公告)号：US20090109996A1
公开(公告)日：2009-04-30
申请号：US11926212
申请日：2007-10-29
申请人： Russell D. Hoover , Eric O. Mejdrich , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Robert A. Shearer
IPC分类号： H04L12/66
CPC分类号： H04L45/00
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，其中每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器的IP间块通信的每个网络接口控制器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式