专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08010750B2 Network on chip that maintains cache coherency with invalidate commands 失效
标题翻译：使用无效命令维护高速缓存一致性的片上网络
公开(公告)号：US08010750B2
公开(公告)日：2011-08-30
申请号：US12015975
申请日：2008-01-17
申请人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich
发明人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich
IPC分类号： G06F12/00
CPC分类号： G06F12/0833
摘要： A network on chip (‘NOC’) including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, wherein the memory communications controller configured to execute a memory access instruction and configured to determine a state of a cache line addressed by the memory access instruction, the state of the cache line being one of shared, exclusive, or invalid; the memory communications controller configured to broadcast an invalidate command to a plurality of IP blocks of the NOC if the state of the cache line is shared; and the memory communications controller configured to transmit an invalidate command only to an IP block that controls a cache where the cache line is stored if the state of the cache line is exclusive.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），其中所述存储器通信控制器被配置为执行存储器访问指令并且被配置为确定由存储器访问指令寻址的高速缓存行，高速缓存行的状态是共享，排他或无效之一; 所述存储器通信控制器被配置为如果所述高速缓存行的状态被共享，则向所述NOC的多个IP块广播无效命令; 以及所述存储器通信控制器被配置为仅当所述高速缓存行的状态是排他性时，将无效命令仅发送到控制高速缓存行存储的高速缓存的IP块。

2. 发明授权

US07917703B2 Network on chip that maintains cache coherency with invalidate commands 失效
标题翻译：使用无效命令维护高速缓存一致性的片上网络
公开(公告)号：US07917703B2
公开(公告)日：2011-03-29
申请号：US11955553
申请日：2007-12-13
申请人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0837 , G06F15/7825
摘要： A network on chip (‘NOC’) comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block coupled to a router through a memory communications controller and a network interface controller, the NOC also including a port on a router of the network through which is received an invalidate command, the invalidate command including an identification of a cache line, the invalidate command representing an instruction to invalidate the cache line, the router configured to send the invalidate command to an IP block served by the router; the router further configured to send the invalidate command horizontally and vertically to neighboring routers if the port is a vertical port; and the router further configured to send the invalidate command only horizontally to neighboring routers if the port is a horizontal port.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器耦合到路由器，NOC 还包括在通过其接收到无效命令的网络的路由器上的端口，包括高速缓存行的标识的无效命令，表示使高速缓存行无效的指令的无效命令，被配置为将无效命令发送到由路由器服务的IP块; 路由器还配置为如果端口是垂直端口，则将无效命令水平和垂直地发送到相邻路由器; 并且该路由器还被配置为仅当该端口是水平端口时才将水平地发送到相邻路由器的invalidate命令。

3. 发明申请

US20090157976A1 Network on Chip That Maintains Cache Coherency With Invalidate Commands 失效
标题翻译：使用无效命令维护缓存一致性的片上网络
公开(公告)号：US20090157976A1
公开(公告)日：2009-06-18
申请号：US11955553
申请日：2007-12-13
申请人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0837 , G06F15/7825
摘要： A network on chip (‘NOC’) that maintains cache coherency with invalidate commands, the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, the NOC also including a port on a router of the network through which is received an invalidate command, the invalidate command including an identification of a cache line, the invalidate command representing an instruction to invalidate the cache line, the router configured to send the invalidate command to an IP block served by the router; the router further configured to send the invalidate command horizontally and vertically to neighboring routers if the port is a vertical port; and the router further configured to send the invalidate command only horizontally to neighboring routers if the port is a horizontal port.
摘要翻译：片上网络（“NOC”）通过无效命令维持高速缓存一致性，NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器适配于路由器通信控制器和网络接口控制器，NOC还包括接收到无效命令的网络的路由器上的端口，包括高速缓存行的标识的无效命令，表示使高速缓存行无效的指令的无效命令路由器被配置为将无效命令发送到由路由器服务的IP块; 路由器还配置为如果端口是垂直端口，则将无效命令水平和垂直地发送到相邻路由器; 并且该路由器还被配置为仅当该端口是水平端口时才将水平地发送到相邻路由器的invalidate命令。

4. 发明申请

US20090187716A1 Network On Chip that Maintains Cache Coherency with Invalidate Commands 失效
标题翻译：使用无效命令保持缓存一致性的片上网络
公开(公告)号：US20090187716A1
公开(公告)日：2009-07-23
申请号：US12015975
申请日：2008-01-17
申请人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich
发明人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich
IPC分类号： G06F12/08
CPC分类号： G06F12/0833
摘要： A network on chip (‘NOC’) that maintains cache coherency, the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, at least one memory communications controller further comprising a cache coherency controller each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, wherein the memory communications controller configured to execute a memory access instruction and configured to determine a state of a cache line addressed by the memory access instruction, the state of the cache line being one of shared, exclusive, or invalid; the memory communications controller configured to broadcast an invalidate command to a plurality of IP blocks of the NOC if the state of the cache line is shared; and the memory communications controller configured to transmit an invalidate command only to an IP block that controls a cache where the cache line is stored if the state of the cache line is exclusive.
摘要翻译：一种保持高速缓存一致性的网络芯片（NOC），NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器适应于路由器，网络接口控制器，至少一个存储器通信控制器，其还包括高速缓存一致性控制器，每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器，其中所述存储器通信控制器被配置执行存储器访问指令并被配置为确定由存储器访问指令寻址的高速缓存行的状态，高速缓存行的状态是共享的，排他的或无效的之一; 所述存储器通信控制器被配置为如果所述高速缓存行的状态被共享，则向所述NOC的多个IP块广播无效命令; 以及所述存储器通信控制器被配置为仅当所述高速缓存行的状态是排他性时，将无效命令仅发送到控制高速缓存行存储的高速缓存的IP块。

5. 发明授权

US07940265B2 Multiple spacial indexes for dynamic scene management in graphics rendering 有权
标题翻译：图形渲染中动态场景管理的多个空间索引
公开(公告)号：US07940265B2
公开(公告)日：2011-05-10
申请号：US11535568
申请日：2006-09-27
申请人： Jeffrey D. Brown , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer
发明人： Jeffrey D. Brown , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer
IPC分类号： G06T15/50 , G06T15/00
CPC分类号： G06T17/005 , G06T1/60 , G06T15/06
摘要： According to embodiments of the invention, separate spatial indexes may be created which correspond to dynamic objects in a three dimensional scene and static objects in the three dimensional scene. By creating separate spatial indexes for static and dynamic objects, only the dynamic spatial index may need to be rebuilt in response to movement or changes in shape of objects in the three dimensional scene. Furthermore, the static and dynamic spatial indexes may be stored in separate portions of an image processing system's memory cache. By storing the static spatial index and the dynamic spatial index in separate portions of the memory cache, the dynamic portion of the memory cache may be updated without affecting the static portion of the spatial index in the memory cache.
摘要翻译：根据本发明的实施例，可以创建对应于三维场景中的动态对象和三维场景中的静态对象的分开的空间索引。通过为静态和动态对象创建单独的空间索引，只有动态空间索引可能需要重建，以响应三维场景中对象的移动或变化。此外，静态和动态空间索引可以存储在图像处理系统的存储器高速缓存的分开的部分中。通过将静态空间索引和动态空间索引存储在存储器高速缓存的分开的部分中，可以更新存储器高速缓存的动态部分而不影响存储器高速缓存中的空间索引的静态部分。

6. 发明授权

US07840757B2 Method and apparatus for providing high speed memory for a processing unit 有权
标题翻译：用于为处理单元提供高速存储器的方法和装置
公开(公告)号：US07840757B2
公开(公告)日：2010-11-23
申请号：US10901600
申请日：2004-07-29
申请人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer , Bruce M. Walk
发明人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer , Bruce M. Walk
IPC分类号： G06F12/00
CPC分类号： G06F12/0888
摘要： Computer systems with direct updating of cache (e.g., primary L1 cache) memories of a processor, such as a central processing unit (CPU) or graphics processing unit (GPU). Special addresses are reserved for high speed memory. Memory access requests involving these reserved addresses are routed directly to the high speed memory. Memory access requests not involving these reserved addresses are routed to memory external to the processor.
摘要翻译：具有直接更新诸如中央处理单元（CPU）或图形处理单元（GPU）的处理器的高速缓存（例如，主要L1高速缓存）存储器的计算机系统。专用地址保留给高速存储器。涉及这些保留地址的存储器访问请求直接路由到高速存储器。不涉及这些保留地址的存储器访问请求被路由到处理器外部的存储器。

7. 发明申请

US20090201302A1 Graphics Rendering On A Network On Chip 失效
标题翻译：网络芯片上的图形渲染
公开(公告)号：US20090201302A1
公开(公告)日：2009-08-13
申请号：US12029647
申请日：2008-02-12
申请人： Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F15/16
CPC分类号： G06T1/20
摘要： Graphics rendering on a network on chip (‘NOC’) including receiving, in the geometry processor, a representation of an object to be rendered; converting, by the geometry processor, the representation of the object to two dimensional primitives; sending, by the geometry processor, the primitives to the plurality of scan converters; converting, by the scan converters, the primitives to fragments, each fragment comprising one or more portions of a pixel; for each fragment: selecting, by the scan converter for the fragment in dependence upon sorting rules, a pixel processor to process the fragment; sending, by the scan converter to the pixel processor, the fragment; and processing, by the pixel processor, the fragment to produce pixels for an image.
摘要翻译：包括在芯片上的图形渲染（“NOC”），包括在几何处理器中接收要呈现的对象的表示; 通过几何处理器将对象的表示转换成二维原语; 由所述几何处理器将所述原语发送到所述多个扫描转换器; 由扫描转换器将原语转换成片段，每个片段包括像素的一个或多个部分; 对于每个片段：由扫描转换器根据排序规则选择片段以处理片段的像素处理器; 由扫描转换器向像素处理器发送片段; 以及由所述像素处理器处理所述片段以产生用于图像的像素。

8. 发明授权

US08018466B2 Graphics rendering on a network on chip 失效
标题翻译：片上网络上的图形渲染
公开(公告)号：US08018466B2
公开(公告)日：2011-09-13
申请号：US12029647
申请日：2008-02-12
申请人： Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G09G5/00 , G06F15/16 , G06F13/14
CPC分类号： G06T1/20
摘要： Graphics rendering on a network on chip (‘NOC’) including receiving, in the geometry processor, a representation of an object to be rendered; converting, by the geometry processor, the representation of the object to two dimensional primitives; sending, by the geometry processor, the primitives to the plurality of scan converters; converting, by the scan converters, the primitives to fragments, each fragment comprising one or more portions of a pixel; for each fragment: selecting, by the scan converter for the fragment in dependence upon sorting rules, a pixel processor to process the fragment; sending, by the scan converter to the pixel processor, the fragment; and processing, by the pixel processor, the fragment to produce pixels for an image.
摘要翻译：包括在芯片上的图形渲染（“NOC”），包括在几何处理器中接收要呈现的对象的表示; 通过几何处理器将对象的表示转换成二维原语; 由所述几何处理器将所述原语发送到所述多个扫描转换器; 由扫描转换器将原语转换成片段，每个片段包括像素的一个或多个部分; 对于每个片段：由扫描转换器根据排序规则选择片段以处理片段的像素处理器; 由扫描转换器向像素处理器发送片段; 以及由所述像素处理器处理所述片段以产生用于图像的像素。

9. 发明申请

US20080074416A1 Multiple Spacial Indexes for Dynamic Scene Management in Graphics Rendering 有权
标题翻译：图形渲染中动态场景管理的多重空间索引
公开(公告)号：US20080074416A1
公开(公告)日：2008-03-27
申请号：US11535568
申请日：2006-09-27
申请人： Jeffrey D. Brown , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer
发明人： Jeffrey D. Brown , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer
IPC分类号： G06T15/40
CPC分类号： G06T17/005 , G06T1/60 , G06T15/06
摘要： According to embodiments of the invention, separate spatial indexes may be created which correspond to dynamic objects in a three dimensional scene and static objects in the three dimensional scene. By creating separate spatial indexes for static and dynamic objects, only the dynamic spatial index may need to be rebuilt in response to movement or changes in shape of objects in the three dimensional scene. Furthermore, the static and dynamic spatial indexes may be stored in separate portions of an image processing system's memory cache. By storing the static spatial index and the dynamic spatial index in separate portions of the memory cache, the dynamic portion of the memory cache may be updated without affecting the static portion of the spatial index in the memory cache.
摘要翻译：根据本发明的实施例，可以创建对应于三维场景中的动态对象和三维场景中的静态对象的分开的空间索引。通过为静态和动态对象创建单独的空间索引，只有动态空间索引可能需要重建，以响应三维场景中对象的移动或变化。此外，静态和动态空间索引可以存储在图像处理系统的存储器高速缓存的分开的部分中。通过将静态空间索引和动态空间索引存储在存储器高速缓存的分开的部分中，可以更新存储器高速缓存的动态部分而不影响存储器高速缓存中的空间索引的静态部分。

10. 发明授权

US08392664B2 Network on chip 有权
标题翻译：网络芯片
公开(公告)号：US08392664B2
公开(公告)日：2013-03-05
申请号：US12118017
申请日：2008-05-09
申请人： Miguel Comparan , Russell D. Hoover , Eric O. Mejdrich
发明人： Miguel Comparan , Russell D. Hoover , Eric O. Mejdrich
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/126
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; and at least one IP block also including a computer processor and an L1, write-through data cache comprising high speed local memory on the IP block, the cache controlled by a cache controller having a cache line replacement policy, the cache controller configured to lock segments of the cache, the computer processor configured to store thread-private data in main memory off the IP block, the computer processor further configured to store thread-private data on a segment of the L1 data cache, the segment locked against replacement upon cache misses under the cache controller's replacement policy, the segment further locked against write-through to main memory.
摘要翻译：包括集成处理器（IP）块，路由器，存储器通信控制器和网络接口控制器的片上网络（NOC）每个IP块通过存储器通信控制器和网络接口控制器适应于路由器; 以及至少一个IP块，其还包括计算机处理器和包括IP块上的高速本地存储器的L1，直通数据高速缓存，由具有高速缓存行替换策略的高速缓存控制器控制的高速缓存，高速缓存控制器被配置为锁定所述计算机处理器被配置为将主存储器中的线程专用数据存储在所述IP块之外，所述计算机处理器还被配置为将线程专用数据存储在所述L1数据高速缓存的段上，所述段被锁定以防止在高速缓存错过了缓存控制器的替换策略，该段进一步锁定到主内存的写入。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式