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1. 发明申请

US20120152296A1 THERMOELECTRIC DEVICE, THERMOELECTIC DEVICE MODULE, AND METHOD OF FORMING THE THERMOELECTRIC DEVICE 审中-公开
标题翻译：热电装置，热电装置模块及形成热电装置的方法
公开(公告)号：US20120152296A1
公开(公告)日：2012-06-21
申请号：US13408153
申请日：2012-02-29
申请人： Moon-Gyu Jang , Myung-Sim Jun , Tae-Moon Roh , Jong-Dae Kim , Tae-Hyoung Zyung
发明人： Moon-Gyu Jang , Myung-Sim Jun , Tae-Moon Roh , Jong-Dae Kim , Tae-Hyoung Zyung
IPC分类号： H01L35/28 , H01L35/34 , B82Y99/00 , B82Y40/00
CPC分类号： H01L35/32 , H01L35/34
摘要： Provided are a thermoelectric device, a thermoelectric device module, and a method of forming the thermoelectric device. The thermoelectric device includes a first conductive type first semiconductor nanowire including at least one first barrier region; a second conductive type second semiconductor nanowire including at least one second barrier region; a first electrode connected to one end of the first semiconductor nanowire; a second electrode connected to one end of the second semiconductor nanowire; and a common electrode connected to the other end of the first semiconductor nanowire and the other end of the second semiconductor nanowire. The first barrier region is greater than the first semiconductor nanowire in thermal conductivity, and the second barrier region is greater than the second semiconductor nanowire in thermal conductivity.
摘要翻译：提供了一种热电装置，热电装置模块和形成热电装置的方法。热电装置包括：第一导电型第一半导体纳米线，其包括至少一个第一阻挡区; 包括至少一个第二阻挡区域的第二导电类型的第二半导体纳米线; 连接到第一半导体纳米线的一端的第一电极; 连接到所述第二半导体纳米线的一端的第二电极; 以及连接到第一半导体纳米线的另一端和第二半导体纳米线的另一端的公共电极。第一阻挡区域的导热率大于第一半导体纳米线，第二阻挡区域的导热率大于第二半导体纳米线。

2. 发明授权

US08026508B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08026508B2
公开(公告)日：2011-09-27
申请号：US12498402
申请日：2009-07-07
申请人： Myung-Sim Jun , Moon-Gyu Jang , Tae-Gon Noh , Tae-Moon Roh
发明人： Myung-Sim Jun , Moon-Gyu Jang , Tae-Gon Noh , Tae-Moon Roh
IPC分类号： H01L33/00 , H01L29/78
CPC分类号： H01L29/122 , B82Y10/00 , H01L31/113 , Y10S977/937 , Y10S977/953
摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a single electron box including a first quantum dot, a charge storage gate on the first quantum dot, and a first gate electrode on the charge storage gate, the charge storage gate exchanging charges with the first quantum dot, the first gate electrode adjusting electric potential of the first quantum dot; and a single electron transistor including a second quantum dot below the first quantum dot, a source, a drain, and a second gate electrode below the second quantum dot, the second quantum dot being capacitively coupled to the first quantum dot, the source contacting one side of the second quantum dot, the drain contacting the other side facing the one side, the second gate electrode adjusting electric potential of the second quantum dot.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括：包括第一量子点的单个电子盒，第一量子点上的电荷存储栅极和电荷存储栅极上的第一栅电极，电荷存储栅极与第一量子点交换电荷，第一量子点栅电极调整第一量子点的电位; 以及包括第一量子点下方的第二量子点的单电子晶体管，位于第二量子点下方的源极，漏极和第二栅电极，第二量子点电容耦合到第一量子点，源极与第一量子点接触所述第二量子点的所述漏极与所述一侧面对的另一侧接触，所述第二栅电极调整所述第二量子点的电位。

3. 发明申请

US20110068326A1 SCHOTTKY BARRIER TUNNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：肖特基BARRIER隧道晶体管及其制造方法
公开(公告)号：US20110068326A1
公开(公告)日：2011-03-24
申请号：US12957146
申请日：2010-11-30
申请人： Moon-Gyu Jang , Yark-Yeon Kim , Chel-Jong Choi , Myung-Sim Jun , Tae-Youb Kim , Seong-Jae Lee
发明人： Moon-Gyu Jang , Yark-Yeon Kim , Chel-Jong Choi , Myung-Sim Jun , Tae-Youb Kim , Seong-Jae Lee
IPC分类号： H01L29/78
CPC分类号： H01L29/8126 , H01L29/66409
摘要： A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.
摘要翻译：肖特基势垒隧道晶体管包括栅极电极和源极和漏极区域。栅电极形成在衬底的沟道区上，以与衬底形成肖特基结。源极和漏极区域形成在暴露于栅电极两侧的衬底中。

4. 发明授权

US07745316B2 Method for fabricating Schottky barrier tunnel transistor 失效
标题翻译：制造肖特基势垒隧道晶体管的方法
公开(公告)号：US07745316B2
公开(公告)日：2010-06-29
申请号：US11930902
申请日：2007-10-31
申请人： Yark-Yeon Kim , Seong-Jae Lee , Moon-Gyu Jang , Tae-Youb Kim , Chel-Jong Choi , Myung-Sim Jun , Byoung-Chul Park
发明人： Yark-Yeon Kim , Seong-Jae Lee , Moon-Gyu Jang , Tae-Youb Kim , Chel-Jong Choi , Myung-Sim Jun , Byoung-Chul Park
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L29/78618 , H01L29/7839
摘要： Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.
摘要翻译：提供一种用于制造肖特基势垒隧道晶体管（SBTT）的方法，其可以从根本上防止由栅极电极的两个侧壁上形成的间隔物的损坏引起的栅极漏电流的产生。一种制造肖特基势垒隧道晶体管的方法，包括：a）在由支撑衬底支撑的掩埋氧化物层上形成硅图案和牺牲图案; b）在暴露于硅图案的两侧的掩埋氧化物层上形成源极/漏极区域，源极/漏极区域由金属层形成并与硅图案的两个侧壁接触; c）去除牺牲图案以暴露硅图案的顶表面; 以及d）在暴露的硅图案上形成栅极绝缘层和栅电极。

5. 发明授权

US07863121B2 Method for fabricating Schottky barrier tunnel transistor 失效
标题翻译：制造肖特基势垒隧道晶体管的方法
公开(公告)号：US07863121B2
公开(公告)日：2011-01-04
申请号：US11800914
申请日：2007-05-08
申请人： Moon-Gyu Jang , Yark-Yeon Kim , Chel-Jong Choi , Myung-Sim Jun , Tae-Youb Kim , Seong-Jae Lee
发明人： Moon-Gyu Jang , Yark-Yeon Kim , Chel-Jong Choi , Myung-Sim Jun , Tae-Youb Kim , Seong-Jae Lee
IPC分类号： H01L21/338
CPC分类号： H01L29/8126 , H01L29/66409
摘要： A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.
摘要翻译：肖特基势垒隧道晶体管包括栅极电极和源极和漏极区域。栅电极形成在衬底的沟道区上，以与衬底形成肖特基结。源极和漏极区域形成在暴露于栅电极两侧的衬底中。

6. 发明申请

US20080132049A1 METHOD FOR FABRICATING SCHOTTKY BARRIER TUNNEL TRANSISTOR 失效
标题翻译：用于制作肖特基栅栏隧道晶体管的方法
公开(公告)号：US20080132049A1
公开(公告)日：2008-06-05
申请号：US11930902
申请日：2007-10-31
申请人： Yark-Yeon KIM , Seong-Jae Lee , Moon-Gyu Jang , Tae-Youb Kim , Chel-Jong Choi , Myung-Sim Jun , Byoung-Chul Park
发明人： Yark-Yeon KIM , Seong-Jae Lee , Moon-Gyu Jang , Tae-Youb Kim , Chel-Jong Choi , Myung-Sim Jun , Byoung-Chul Park
IPC分类号： H01L21/334
CPC分类号： H01L29/78618 , H01L29/7839
摘要： Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.
摘要翻译：提供一种用于制造肖特基势垒隧道晶体管（SBTT）的方法，其可以从根本上防止由栅极电极的两个侧壁上形成的间隔物的损坏引起的栅极漏电流的产生。一种制造肖特基势垒隧道晶体管的方法，包括：a）在由支撑衬底支撑的掩埋氧化物层上形成硅图案和牺牲图案; b）在暴露于硅图案的两侧的掩埋氧化物层上形成源极/漏极区域，源极/漏极区域由金属层形成并与硅图案的两个侧壁接触; c）去除牺牲图案以暴露硅图案的顶表面; 以及d）在暴露的硅图案上形成栅极绝缘层和栅电极。

7. 发明申请

US20080121868A1 Schottky barrier tunnel transistor and method for fabricating the same 失效
标题翻译：肖特基势垒隧道晶体管及其制造方法
公开(公告)号：US20080121868A1
公开(公告)日：2008-05-29
申请号：US11800914
申请日：2007-05-08
申请人： Moon-Gyu Jang , Yark-Yeon Kim , Chel-Jong Choi , Myung-Sim Jun , Tae-Youb Kim , Seong-Jae Lee
发明人： Moon-Gyu Jang , Yark-Yeon Kim , Chel-Jong Choi , Myung-Sim Jun , Tae-Youb Kim , Seong-Jae Lee
IPC分类号： H01L29/47 , H01L21/338
CPC分类号： H01L29/8126 , H01L29/66409
摘要： A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.
摘要翻译：肖特基势垒隧道晶体管包括栅极电极和源极和漏极区域。栅电极形成在衬底的沟道区上，以与衬底形成肖特基结。源极和漏极区域形成在暴露于栅电极两侧的衬底中。

8. 发明授权

US08529750B2 Apparatus and method for detecting biomolecules 有权
标题翻译：用于检测生物分子的装置和方法
公开(公告)号：US08529750B2
公开(公告)日：2013-09-10
申请号：US13062146
申请日：2008-11-20
申请人： Chil-Seong Ah , Ansoon Kim , Chan-Woo Park , Chang-Geun Ahn , Jong-Heon Yang , In-Bok Baek , Taeyoub Kim , HyeKyoung Yang , Gun-Yong Sung , Seon-Hee Park , Han-Young Yu , Moon-Gyu Jang
发明人： Chil-Seong Ah , Ansoon Kim , Chan-Woo Park , Chang-Geun Ahn , Jong-Heon Yang , In-Bok Baek , Taeyoub Kim , HyeKyoung Yang , Gun-Yong Sung , Seon-Hee Park , Han-Young Yu , Moon-Gyu Jang
IPC分类号： G01N27/414
CPC分类号： G01N33/54373 , B01L3/502761 , B01L2200/143 , B01L2300/0636 , B01L2300/0645 , B01L2300/0867 , B01L2300/163 , B01L2400/0415 , G01N27/4145
摘要： Provided are an apparatus and method for detecting biomolecules. The apparatus includes a FET having a substrate, a source electrode, a drain electrode, a channel region between the source and drain electrodes, and probe molecules fixed to the channel region, wherein the source and drain electrodes are separated on the substrate, a microfluid supplier selectively supplying one of a reference buffer solution of low ionic concentration and a reaction solution of high ionic concentration containing target molecules, to the channel region of the FET to which the probe molecules are fixed, and a biomolecule detector detecting the target molecules by measuring a first current value of the channel region of the FET, and a second current value of the channel region of the FET to which the target molecules and the probe molecules that bind to each other in the reaction solution of high ionic concentration are fixed.
摘要翻译：提供了用于检测生物分子的装置和方法。该装置包括具有基板，源电极，漏电极，源极和漏极之间的沟道区以及固定到沟道区的探针分子的FET，其中源极和漏极在衬底上分离，微流体供应商选择性地将低离子浓度的参考缓冲溶液和含有靶分子的高离子浓度的反应溶液中的一种提供给探针分子固定的FET的通道区域，以及通过测量来检测靶分子的生物分子检测器 FET的沟道区域的第一电流值和在高离子浓度的反应溶液中彼此结合的靶分子和探针分子的FET的沟道区域的第二电流值是固定的。

9. 发明申请

US20080128760A1 SCHOTTKY BARRIER NANOWIRE FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：肖特基屏障纳米级场效应晶体管及其制造方法
公开(公告)号：US20080128760A1
公开(公告)日：2008-06-05
申请号：US11948664
申请日：2007-11-30
申请人： Myungsim Jun , Moon-Gyu Jang , Yark-Yeon Kim , Chel-Jong Choi , Taeyoub Kim , Seongjae Lee
发明人： Myungsim Jun , Moon-Gyu Jang , Yark-Yeon Kim , Chel-Jong Choi , Taeyoub Kim , Seongjae Lee
IPC分类号： H01L21/338 , H01L29/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/458 , H01L29/775 , H01L29/7839 , H01L29/78681 , H01L29/7869 , H01L29/78696 , H01L51/0048 , H01L51/0508
摘要： Provided is a Schottky barrier nanowire field effect transistor, which has source/drain electrodes formed of metal silicide and a channel formed of a nanowire, and a method for fabricating the same. The Schottky barrier nanowire field effect transistor includes: a channel suspended over a substrate and including a nanowire; metal silicide source/drain electrodes electrically connected to both ends of the channel over the substrate; a gate electrode disposed to surround the channel; and a gate insulation layer disposed between the channel and the gate electrode.
摘要翻译：提供了一种肖特基势垒纳米线场效应晶体管及其制造方法，该晶体管具有由金属硅化物形成的源/漏电极和由纳米线形成的沟道。肖特基势垒纳米线场效应晶体管包括：悬浮在衬底上并包括纳米线的沟道; 金属硅化物源/漏电极，电连接到沟道的两端，在衬底上; 设置成围绕所述通道的栅电极; 以及设置在通道和栅电极之间的栅极绝缘层。

10. 发明申请

US20110000517A1 THERMOELECTRIC DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：热电装置及其制造方法
公开(公告)号：US20110000517A1
公开(公告)日：2011-01-06
申请号：US12632403
申请日：2009-12-07
申请人： Young-Sam Park , Moon-Gyu Jang , Taehyoung Zyung , Younghoon Hyun , Myungsim Jun
发明人： Young-Sam Park , Moon-Gyu Jang , Taehyoung Zyung , Younghoon Hyun , Myungsim Jun
IPC分类号： H01L35/20 , H01L35/00 , B05D5/12 , H01L35/34
CPC分类号： H01L35/32 , H01L35/26 , H01L35/34
摘要： A thermoelectric device is provided. The thermoelectric device includes first and second electrodes, a first leg, a second leg, and a common electrode. The first leg is disposed on the first electrode and includes one or more first semiconductor pattern and one or more first barrier patterns. The second leg is disposed on the second electrode and includes one or more second semiconductor pattern and one or more second barrier patterns. The common electrode is disposed on the first leg and the second leg. Herein, the first barrier pattern has a lower thermal conductivity than the first semiconductor pattern, and the second barrier pattern has a lower thermal conductivity than the second semiconductor pattern. The first/second barrier pattern has a higher electric conductivity than the first/second semiconductor pattern. The first/second barrier pattern forms an ohmic contact with the first/second semiconductor pattern.
摘要翻译：提供了一种热电装置。热电装置包括第一和第二电极，第一支腿，第二支腿和公共电极。第一支腿设置在第一电极上并且包括一个或多个第一半导体图案和一个或多个第一屏障图案。第二腿设置在第二电极上，并且包括一个或多个第二半导体图案和一个或多个第二屏障图案。公共电极设置在第一腿部和第二腿部上。这里，第一阻挡图案的热导率比第一半导体图案低，第二阻挡图案的热导率比第二半导体图案低。第一/第二阻挡图案具有比第一/第二半导体图案更高的导电性。第一/第二屏障图案与第一/第二半导体图案形成欧姆接触。

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