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1. 发明授权

US07957217B2 Method of controlling internal voltage and multi-chip package memory prepared using the same 有权
标题翻译：控制内部电压的方法和使用其制备的多芯片封装存储器
公开(公告)号：US07957217B2
公开(公告)日：2011-06-07
申请号：US12266716
申请日：2008-11-07
申请人： Moon-sook Park , Hoe-ju Chung , Jung-bae Lee
发明人： Moon-sook Park , Hoe-ju Chung , Jung-bae Lee
IPC分类号： G11C8/00
CPC分类号： G11C5/147 , G11C5/04
摘要： The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device.
摘要翻译：本发明一般涉及一种多芯片封装（MCP）存储器件，尤其涉及但不限于具有减小尺寸的MCP存储器件。在一个实施例中，MCP存储器件包括：传送存储器芯片; 以及多个存储器芯片，其耦合到所述传送存储器芯片，所述多个存储器芯片中的每一个包括内部电压产生电路，所述传送存储器芯片被配置为从所述MCP存储器设备的外部接收多个命令信号，所述传送存储器芯片还被配置为基于所述多个命令信号将多个控制信号输出到所述多个存储器芯片。本发明的实施例还涉及一种控制MCP存储器件的内部电压的方法。

2. 发明申请

US20070090866A1 Duty cycle correction circuit, clock generation circuits, semiconductor devices using the same, and method for generating clock signal 有权
标题翻译：占空比校正电路，时钟发生电路，使用其的半导体器件，以及用于产生时钟信号的方法
公开(公告)号：US20070090866A1
公开(公告)日：2007-04-26
申请号：US11496447
申请日：2006-08-01
申请人： Moon-sook Park , Kyu-hyoun Kim
发明人： Moon-sook Park , Kyu-hyoun Kim
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00052 , H03L7/08 , H03L7/0812 , H03L7/0891
摘要： A semiconductor device and method of generating clock signals where a phase lock loop (PLL), or a delay lock loop (DLL), comprises a duty cycle correction circuit (DCC) having a shared charge pump and a plurality of amplification parts. The plurality of amplification parts generate internal clock signals. The shared charge pump adjusts voltage level of control signal (VC) in response to the internal clock signals and provides the control signal VC to each of the amplification parts.
摘要翻译：一种产生时钟信号的半导体器件和方法，其中锁相环（PLL）或延迟锁环（DLL）包括具有共享电荷泵和多个放大部分的占空比校正电路（DCC）。多个放大部分产生内部时钟信号。共享电荷泵响应于内部时钟信号调节控制信号（VC）的电压电平，并向每个放大部分提供控制信号VC。

3. 发明授权

US07567106B2 Duty cycle correction circuit, clock generation circuits, semiconductor devices using the same, and method for generating clock signal 有权
标题翻译：占空比校正电路，时钟发生电路，使用其的半导体器件，以及用于产生时钟信号的方法
公开(公告)号：US07567106B2
公开(公告)日：2009-07-28
申请号：US11496447
申请日：2006-08-01
申请人： Moon-sook Park , Kyu-hyoun Kim
发明人： Moon-sook Park , Kyu-hyoun Kim
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00052 , H03L7/08 , H03L7/0812 , H03L7/0891
摘要： A semiconductor device and method of generating clock signals where a phase lock loop (PLL), or a delay lock loop (DLL), comprises a duty cycle correction circuit (DCC) having a shared charge pump and a plurality of amplification parts. The plurality of amplification parts generate internal clock signals. The shared charge pump adjusts voltage level of control signal (VC) in response to the internal clock signals and provides the control signal VC to each of the amplification parts.
摘要翻译：一种产生时钟信号的半导体器件和方法，其中锁相环（PLL）或延迟锁环（DLL）包括具有共享电荷泵和多个放大部分的占空比校正电路（DCC）。多个放大部分产生内部时钟信号。共享电荷泵响应于内部时钟信号调节控制信号（VC）的电压电平，并向每个放大部分提供控制信号VC。

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