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1. 发明授权

US07417902B2 Input circuit for a memory device, and a memory device and memory system employing the input circuit 有权
标题翻译：用于存储器件的输入电路，以及采用该输入电路的存储器件和存储器系统
公开(公告)号：US07417902B2
公开(公告)日：2008-08-26
申请号：US11325343
申请日：2006-01-05
申请人： Moon-Sook Park , Kyu-hyoun Kim
发明人： Moon-Sook Park , Kyu-hyoun Kim
IPC分类号： G11C7/06
CPC分类号： G11C7/1078 , G11C7/1084 , G11C2207/2254
摘要： In one embodiment, the input circuit includes a receiver circuit that generates a data signal based on a pair of differential data signals. A detecting circuit detects an offset voltage between the pair of differential data signals, and an adjusting circuit adjusts operation of the receiver to reduce a magnitude of the detected offset voltage based on the detected offset voltage.
摘要翻译：在一个实施例中，输入电路包括基于一对差分数据信号产生数据信号的接收器电路。检测电路检测一对差分数据信号之间的偏移电压，并且调整电路基于检测到的偏移电压来调整接收机的操作以减小检测到的偏移电压的幅度。

2. 发明申请

US20070090866A1 Duty cycle correction circuit, clock generation circuits, semiconductor devices using the same, and method for generating clock signal 有权
标题翻译：占空比校正电路，时钟发生电路，使用其的半导体器件，以及用于产生时钟信号的方法
公开(公告)号：US20070090866A1
公开(公告)日：2007-04-26
申请号：US11496447
申请日：2006-08-01
申请人： Moon-sook Park , Kyu-hyoun Kim
发明人： Moon-sook Park , Kyu-hyoun Kim
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00052 , H03L7/08 , H03L7/0812 , H03L7/0891
摘要： A semiconductor device and method of generating clock signals where a phase lock loop (PLL), or a delay lock loop (DLL), comprises a duty cycle correction circuit (DCC) having a shared charge pump and a plurality of amplification parts. The plurality of amplification parts generate internal clock signals. The shared charge pump adjusts voltage level of control signal (VC) in response to the internal clock signals and provides the control signal VC to each of the amplification parts.
摘要翻译：一种产生时钟信号的半导体器件和方法，其中锁相环（PLL）或延迟锁环（DLL）包括具有共享电荷泵和多个放大部分的占空比校正电路（DCC）。多个放大部分产生内部时钟信号。共享电荷泵响应于内部时钟信号调节控制信号（VC）的电压电平，并向每个放大部分提供控制信号VC。

3. 发明申请

US20070058454A1 Input circuit for a memory device, and a memory device and memory system employing the input circuit 有权
标题翻译：用于存储器件的输入电路，以及采用该输入电路的存储器件和存储器系统
公开(公告)号：US20070058454A1
公开(公告)日：2007-03-15
申请号：US11325343
申请日：2006-01-05
申请人： Moon-Sook Park , Kyu-hyoun Kim
发明人： Moon-Sook Park , Kyu-hyoun Kim
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1084 , G11C2207/2254
摘要： In one embodiment, the input circuit includes a receiver circuit that generates a data signal based on a pair of differential data signals. A detecting circuit detects an offset voltage between the pair of differential data signals, and an adjusting circuit adjusts operation of the receiver to reduce a magnitude of the detected offset voltage based on the detected offset voltage.
摘要翻译：在一个实施例中，输入电路包括基于一对差分数据信号产生数据信号的接收器电路。检测电路检测一对差分数据信号之间的偏移电压，并且调整电路基于检测到的偏移电压来调整接收机的操作以减小检测到的偏移电压的幅度。

4. 发明授权

US07567106B2 Duty cycle correction circuit, clock generation circuits, semiconductor devices using the same, and method for generating clock signal 有权
标题翻译：占空比校正电路，时钟发生电路，使用其的半导体器件，以及用于产生时钟信号的方法
公开(公告)号：US07567106B2
公开(公告)日：2009-07-28
申请号：US11496447
申请日：2006-08-01
申请人： Moon-sook Park , Kyu-hyoun Kim
发明人： Moon-sook Park , Kyu-hyoun Kim
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00052 , H03L7/08 , H03L7/0812 , H03L7/0891
摘要： A semiconductor device and method of generating clock signals where a phase lock loop (PLL), or a delay lock loop (DLL), comprises a duty cycle correction circuit (DCC) having a shared charge pump and a plurality of amplification parts. The plurality of amplification parts generate internal clock signals. The shared charge pump adjusts voltage level of control signal (VC) in response to the internal clock signals and provides the control signal VC to each of the amplification parts.
摘要翻译：一种产生时钟信号的半导体器件和方法，其中锁相环（PLL）或延迟锁环（DLL）包括具有共享电荷泵和多个放大部分的占空比校正电路（DCC）。多个放大部分产生内部时钟信号。共享电荷泵响应于内部时钟信号调节控制信号（VC）的电压电平，并向每个放大部分提供控制信号VC。

5. 发明授权

US08718216B2 Digital phase detector with zero phase offset 失效
公开(公告)号：US08718216B2
公开(公告)日：2014-05-06
申请号：US13242053
申请日：2011-09-23
申请人： Daniel M. Dreps , Kyu-hyoun Kim , Glen A. Wiedemeier
发明人： Daniel M. Dreps , Kyu-hyoun Kim , Glen A. Wiedemeier
IPC分类号： H03D3/24
CPC分类号： H04L7/0037 , H03L7/0814 , H03L7/085 , H03L7/089
摘要： An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

6. 发明授权

US08639874B2 Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device 失效
标题翻译：通过向DRAM设备发出电源开/关命令，对缓冲DIMM上的备用DRAM进行电源管理
公开(公告)号：US08639874B2
公开(公告)日：2014-01-28
申请号：US12341515
申请日：2008-12-22
申请人： Warren Edward Maule , Kevin C. Gower , Kyu-hyoun Kim , Dustin James VanStee
发明人： Warren Edward Maule , Kevin C. Gower , Kyu-hyoun Kim , Dustin James VanStee
IPC分类号： G06F12/06
CPC分类号： G11C5/06 , G11C5/04 , G11C5/14 , G11C11/4074
摘要： A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.
摘要翻译：一种具有一个或多个具有内部存储器阵列的半导体存储器件的计算机存储器，所述内部存储器阵列包括排列成行和列的矩阵的多个半导体动态随机存取存储器（DRAM）单元，并被提供为这种存储器的存储器模块等级在基板上的一个或多个所述半导体存储器件的DIMM上布置的阵列中的器件，其可以经由存储器件数据接口耦合到作为存储器子系统的存储器系统，每个所述存储器件具有低功率闭合 - 可以使用公共存储器数据接口激活。通过数据接口对DRAM的功率的控制问题DRAM功率控制命令的两个命令解码，功率状态程序信号和功率状态复位信号作为功率状态控制命令来控制所述DRAM的功率状态，并激活用于将存储器单元作为正常的有源或备用设备读/写。

7. 发明申请

US20130313705A1 IMPLEMENTING DECOUPLING DEVICES INSIDE A TSV DRAM STACK 失效
标题翻译：在TSV DRAM堆栈中实现解码器件
公开(公告)号：US20130313705A1
公开(公告)日：2013-11-28
申请号：US13477371
申请日：2012-05-22
申请人： Joab D. Henderson , Kyu-hyoun Kim , Warren E. Maule , Kenneth L. Wright
发明人： Joab D. Henderson , Kyu-hyoun Kim , Warren E. Maule , Kenneth L. Wright
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/498 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L2224/0401 , H01L2224/05009 , H01L2224/05027 , H01L2224/13014 , H01L2224/13021 , H01L2224/13025 , H01L2224/131 , H01L2224/14051 , H01L2224/1411 , H01L2224/1613 , H01L2224/16146 , H01L2224/17106 , H01L2224/73204 , H01L2225/06513 , H01L2225/06541 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
摘要： A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled with a conducting material. A layer of glass is grown on both the top and bottom of the DRAM providing an insulator. A layer of metal is grown on each glass layer providing a conductor. The metal and glass layers are etched through to TSVs with a gap provided around the perimeter of via pads. A respective solder ball is formed on the TSVs to connect to another DRAM chip in the DRAM TSV stack. The metal layers are connected to at least one TSV by one respective solder ball and are connected to a voltage source and a dielectric is inserted between the metal layers in the DRAM TSV stack to complete the decoupling capacitor.
摘要翻译：提供了一种用于在DRAM TSV堆栈内实现去耦电容器的方法和结构。形成有多个完全延伸穿过衬底并填充有导电材料的TSV的DRAM。在提供绝缘体的DRAM的顶部和底部都生长玻璃层。在提供导体的每个玻璃层上生长一层金属。金属和玻璃层被蚀刻到具有围绕通孔焊盘的周边设置的间隙的TSV。在TSV上形成相应的焊球以连接到DRAM TSV堆叠中的另一个DRAM芯片。金属层通过一个相应的焊球连接到至少一个TSV，并且连接到电压源，并且电介质插入在DRAM TSV堆叠中的金属层之间以完成去耦电容器。

8. 发明授权

US08343804B2 Implementing multiple different types of dies for memory stacking 有权
标题翻译：实现多种不同类型的模具进行内存堆叠
公开(公告)号：US08343804B2
公开(公告)日：2013-01-01
申请号：US13364346
申请日：2012-02-02
申请人： Paul W. Coteus , Kyu-hyoun Kim
发明人： Paul W. Coteus , Kyu-hyoun Kim
IPC分类号： H01L21/00
CPC分类号： H01L24/73 , H01L23/481 , H01L24/06 , H01L24/48 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/06181 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/10253 , H01L2924/1434 , H01L2924/15311 , H01L2224/45099 , H01L2924/00
摘要： A method and structure are provided for implementing multiple different types of dies for memory stacking. A common wafer is provided with a predefined reticle type. The reticle type includes a plurality of arrays, and a plurality of periphery segments. A plurality of through-silicon-vias (TSVs) is placed at boundaries between array and periphery segments. Multiple different types of dies for memory stacking are obtained based upon selected scribing of the dies from the common wafer.
摘要翻译：提供了一种用于实现用于存储器堆叠的多种不同类型的管芯的方法和结构。普通晶片具有预定的掩模版类型。标线型包括多个阵列和多个外围段。多个通硅通孔（TSV）被放置在阵列和外围段之间的边界处。基于从公共晶片选择划线的模具，获得用于存储器堆叠的多种不同类型的管芯。

9. 发明申请

US20120151131A1 MEMORY SYSTEM WITH A PROGRAMMABLE REFRESH CYCLE 有权
标题翻译：具有可编程刷新周期的存储器系统
公开(公告)号：US20120151131A1
公开(公告)日：2012-06-14
申请号：US12963797
申请日：2010-12-09
申请人： Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Vipin Patel
发明人： Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Vipin Patel
IPC分类号： G06F12/00 , G11C11/406
CPC分类号： G11C11/406 , G11C2211/4061 , G11C2211/4065
摘要： A memory system with a programmable refresh cycle including a memory device that includes a memory array of memory cells and refresh circuitry that is in communication with the memory array and with a memory controller. The refresh circuitry is configured to receive a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is programmable.
摘要翻译：一种具有可编程刷新周期的存储器系统，包括存储器件，该存储器件包括与存储器阵列和存储器控制器通信的存储器单元的存储器阵列和刷新电路。刷新电路被配置为响应于接收到刷新命令从存储器控制器接收刷新命令并且用于刷新存储器件中的多个存储器单元。响应于接收刷新命令刷新的存储器单元的数量是可编程的。

10. 发明申请

US20110272788A1 Computer system wafer integrating different dies in stacked master-slave structures 审中-公开
标题翻译：在堆叠的主从结构中集成不同模具的计算机系统晶片
公开(公告)号：US20110272788A1
公开(公告)日：2011-11-10
申请号：US12777177
申请日：2010-05-10
申请人： Kyu-hyoun Kim , Paul Coteus
发明人： Kyu-hyoun Kim , Paul Coteus
IPC分类号： H01L29/06 , H01L21/00
CPC分类号： H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541
摘要： A stacked 3D integrated circuit structure is manufactured with a common image design for dies which allows diced master dies to cut from the common wafer and diced slave dies cut to be cut from a wafer which has the common image design. In an embodiment is stacked to form a wafer-to-wafer 3D stack before dicing. Master and slave elements which are used for only one kind of separated individual integrated circuit dies which are located along die edges and at die centers before dicing separation of individual integrated circuit chips. A master wafer is shifted ½ way across a die to make cutting along a kerf line effective to provide both master and slave dies. Multiple slaves can be stacked and coupled to a master die which acts as a bus master when attached to a bus to which only the master die is directly connected. The use of a common wafer design minimizes cost of manufacture of chips destined to be stacked as 3D integrated circuits.
摘要翻译：制造堆叠的3D集成电路结构，其具有用于管芯的公共图像设计，其允许切割的主管芯从公共晶片切割并切割成具有共同图像设计的晶片切割的切割从属裸片。在一个实施例中，在切割之前堆叠以形成晶片到晶片3D堆叠。主单元和从元件仅用于单个集成电路芯片切割分离之前沿着芯片边缘和模具中心位置的一种分离的单独集成电路管芯。主晶片沿模具移动1/2路，以便沿着切割线进行切割有效地提供主模和从模。多个从器件可以堆叠并耦合到主引脚，当连接到仅母模直接连接的总线时，主器件用作总线主器件。使用普通晶圆设计可最大限度地降低作为3D集成电路堆叠的芯片的制造成本。

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