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1. 发明申请

US20190173479A1 SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC), RADAR UNIT AND METHOD FOR IMPROVING HARMONIC DISTORTION PERFORMANCE 审中-公开
公开(公告)号：US20190173479A1
公开(公告)日：2019-06-06
申请号：US16145741
申请日：2018-09-28
申请人： NXP B.V.
发明人： Vladislav Dyachenko , Erwin Janssen , Yu Lin , Athon Zanikopoulos
IPC分类号： H03M1/06 , G01S7/35
摘要： A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: a track and hold circuit (414) configured to sample an analog input signal (410); a comparator (416) coupled to the track and hold circuit and configured to compare the sampled analog input signal (410) with a DAC (444) output voltage; and a feedback path (422) that comprises a digital-to-analog converter, DAC, (444) configured to generate the reference voltage that approximates the input analog signal (410). The SAR ADC (400) further includes a dither circuit (468) coupled to or located in the feedback path (422) and arranged to add a dither signal at an input of the DAC (444) in a first time period and subtract the dither signal from the output digital signal routed via the feedback path (422) and input of the DAC (444) in a second time period during a conversion phase of the SAR ADC (400).

2. 发明申请

US20190149162A1 SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER, ELECTRONIC DEVICE AND METHOD THEREFOR 审中-公开
公开(公告)号：US20190149162A1
公开(公告)日：2019-05-16
申请号：US16119117
申请日：2018-08-31
申请人： NXP B.V.
发明人： Yu Lin , Erwin Janssen , Vladislav Dyachenko
IPC分类号： H03M1/38 , H03M1/10 , G01S13/06
CPC分类号： H03M1/38 , G01S13/06 , H03M1/1004 , H03M1/1028 , H03M1/181 , H03M1/187 , H03M1/462
摘要： A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460). The DAC (430) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller (418) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC (430) and the digital signal reconstruction circuit (450) to implement a small signal mapping mode of operation.

3. 发明申请

US20160238998A1 TIME TO DIGITAL CONVERTER AND PHASE LOCKED LOOP 审中-公开
标题翻译：数字转换器和相位锁定环路
公开(公告)号：US20160238998A1
公开(公告)日：2016-08-18
申请号：US15041202
申请日：2016-02-11
申请人： NXP B.V.
发明人： Nenad Pavlovic , Vladislav Dyachenko , Tarik Saric
IPC分类号： G04F10/00 , H03L7/099 , H03L7/197 , H03M1/38
CPC分类号： G04F10/005 , G01S7/02 , G01S7/35 , G01S13/32 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03L7/085 , H03L7/0992 , H03L7/1974 , H03L7/1976 , H03M1/38
摘要： A time to digital converter (10) is disclosed. The time to digital converter (10) comprises: a synchronisation block (20) configured to output a voltage pulse (110) with duration based on a time difference between a reference oscillating signal (101) and an input oscillating signal (107); a charge pump (41) arranged to receive the voltage pulse (110) and to convert the voltage pulse into a current pulse; an integrator (50) comprising an integrator capacitor (24, 25), the integrator (50) being configured to receive the current pulse (110) and integrate the current pulse (110) as a charge on the integrator capacitor (24, 25), resulting in an integrator output voltage (115); and a successive approximation register (40) configured to determine the integrator output voltage (115) with respect to a reference voltage by adjusting the charge on the integrator capacitor (24, 25) so as to reduce the integrator output voltage (115) to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage (115) as a digital signal (125). A phase locked loop comprising the time to digital converter (10) is disclosed.
摘要翻译：公开了一种数字转换器（10）。数字转换器（10）的时间包括：同步块（20），被配置为基于参考振荡信号（101）和输入振荡信号（107）之间的时间差输出具有持续时间的电压脉冲（110）; 布置成接收电压脉冲（110）并将电压脉冲转换成电流脉冲的电荷泵（41）; 积分器（50），包括积分器电容器（24,25），所述积分器（50）被配置为接收所述电流脉冲（110）并且将所述电流脉冲（110）作为所述积分器电容器（24,25）上的电荷进行积分，，导致积分器输出电压（115）; 以及逐次逼近寄存器（40），被配置为通过调整积分电容器（24,25）上的电荷来确定相对于参考电压的积分器输出电压（115），以便将积分器输出电压（115）减小到通过逐次逼近的参考电压的最低有效位（D0），并且被配置为输出所确定的积分器输出电压（115）作为数字信号（125）。公开了一种包括时间到数字转换器（10）的锁相环。

4. 发明授权

US10826387B2 Charge pump and method for operating a charge pump 有权
公开(公告)号：US10826387B2
公开(公告)日：2020-11-03
申请号：US16201088
申请日：2018-11-27
申请人： NXP B.V.
发明人： Vladislav Dyachenko , Nenad Pavlovic
IPC分类号： H02M3/07 , H03L7/089
摘要： Embodiments of a method for operating a charge pump and a charge pump are disclosed. In an embodiment, a method for operating a charge pump involves during a first operating phase of the charge pump, setting a first current source of the charge pump according to a second current source of the charge pump, and, during a second operating phase of the charge pump that is subsequent to the first operating phase, providing current from the first current source to a load of the charge pump.

5. 发明授权

US10768290B2 Method and apparatus for generating a frequency estimation signal 有权
公开(公告)号：US10768290B2
公开(公告)日：2020-09-08
申请号：US15835186
申请日：2017-12-07
申请人： NXP B.V.
发明人： Yu Lin , Erwin Janssen , Konstantinos Doris , Vladislav Dyachenko , Athon Zanikopoulos
IPC分类号： G01S13/34 , G06F1/02 , H03D7/14 , H03J3/04 , G01R23/04
摘要： A frequency estimation signal generator component arranged to receive an input frequency signal and to generate therefrom a frequency estimation signal. The frequency estimation signal generator component comprises a counter component arranged to sequentially output a sequence of control signal patterns over a plurality of digital control signals under the control of an oscillating signal derived from the received input frequency signal terns. The frequency estimation signal generator further comprises a continuous waveform generator component arranged to receive the plurality of digital control signals and a weighted analogue signal for each of the received digital control signals, and to output a continuous waveform signal comprising a sum of the weighted analogue signals for which the corresponding digital control signals comprise an asserted logical state. The frequency conversion component is arranged to derive the frequency estimation signal from the continuous waveform signal output by the continuous waveform generator component.

6. 发明授权

US10191453B2 Time to digital converter and phase locked loop 有权
公开(公告)号：US10191453B2
公开(公告)日：2019-01-29
申请号：US15041202
申请日：2016-02-11
申请人： NXP B.V.
发明人： Nenad Pavlovic , Vladislav Dyachenko , Tarik Saric
IPC分类号： G04F10/00 , H03C3/09 , H03L7/197 , H03L7/085 , H03L7/099 , H03M1/38 , G01S7/02 , G01S7/35 , G01S13/32 , G01S13/00
摘要： A time to digital converter may include a synchronization block configured to output a voltage pulse with duration based on a time difference between a reference oscillating signal and an input oscillating signal; a charge pump arranged to receive the voltage pulse and to convert the voltage pulse into a current pulse; an integrator comprising an integrator capacitor, the integrator being configured to receive the current pulse and integrate the current pulse as a charge on the integrator capacitor, resulting in an integrator output voltage; and a successive approximation register configured to determine the integrator output voltage with respect to a reference voltage by adjusting the charge on the integrator capacitor so as to reduce the integrator output voltage to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage as a digital signal.

7. 发明授权

US10790850B1 Signal amplitude aware dithering method for enhancing small signal linearity in an analog-to-digital converter 有权
公开(公告)号：US10790850B1
公开(公告)日：2020-09-29
申请号：US16456365
申请日：2019-06-28
申请人： NXP B.V.
发明人： Yu Lin , Vladislav Dyachenko
IPC分类号： H03M1/20 , H03M3/00 , H03M1/46
摘要： An analog-to-digital converter (ADC) and a method are disclosed. The ADC includes dithering circuitry. The dithering circuitry includes a signal level detector, a dither amplitude controller, a random code generator, and a dither digital-to-analog converter (DAC). The signal level detector receives the analog input signal and provides amplitude level information associated with the analog input signal. The dither amplitude controller receives the amplitude level information from the signal level detector, and provides a control signal. The dither amplitude controller varies the control signal based on the amplitude level information. The dither DAC receives the control signal from the dither amplitude controller and a pseudo-noise (PN) signal from the random code generator, and provides the dither signal based on the control signal. The dither signal varies based on an amplitude level of the analog input signal.

8. 发明授权

US10581439B1 Clock synchronization in an ADPLL 有权
公开(公告)号：US10581439B1
公开(公告)日：2020-03-03
申请号：US16457845
申请日：2019-06-28
申请人： NXP B.V.
发明人： Nenad Pavlovic , Vladislav Dyachenko
IPC分类号： G06F1/10 , H03L7/089 , H03L7/087 , H03M1/46 , G04F10/00 , H03L7/099
摘要： Embodiments of a clock synchronization unit of an All Digital Phase-Locked Loop (ADPLL), a successive approximation register (SAR) Time-to-Digital Converter (TDC) of an ADPLL and a method for clock synchronization in an ADPLL are disclosed. In one embodiment, a clock synchronization unit of an ADPLL includes a two-flop synchronizer, a phase frequency detector (PFD) connected to the two-flop synchronizer, and a synchronization control circuit configured to control the two-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal and to control the two-flop synchronizer and the PFD to replace a performance of the clock synchronization between the reference clock input signal and the divided clock input signal with a PFD operation. Other embodiments are also described.

9. 发明授权

US10469095B2 Successive approximation register analog-to-digital converter, electronic device and method therefor 有权
公开(公告)号：US10469095B2
公开(公告)日：2019-11-05
申请号：US16119117
申请日：2018-08-31
申请人： NXP B.V.
发明人： Yu Lin , Erwin Janssen , Vladislav Dyachenko
IPC分类号： H03M1/38 , H03M1/18 , G01S13/06 , H03M1/10 , H03M1/46
摘要： A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460). The DAC (430) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller (418) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC (430) and the digital signal reconstruction circuit (450) to implement a small signal mapping mode of operation.

10. 发明授权

US09584177B2 Time to digital converter and phase locked loop 有权
标题翻译：时间到数字转换器和锁相环
公开(公告)号：US09584177B2
公开(公告)日：2017-02-28
申请号：US15041217
申请日：2016-02-11
申请人： NXP B.V.
发明人： Nenad Pavlovic , Vladislav Dyachenko , Tarik Saric
IPC分类号： H04L1/00 , H04B1/7073 , H03L7/197 , H04B1/69 , H03C3/09
CPC分类号： H04B1/7073 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03C3/0991 , H03L7/1976 , H04B2001/6912 , H04B2201/7073
摘要： A phase locked loop is disclosed having a frequency controlled oscillator, a feedback path, a time to digital converter and a memory. The frequency controlled oscillator comprises a first control input for varying the frequency of the output of the frequency controlled oscillator so as to track a reference frequency and a second control input for modulating the frequency of the output signal so as to produce a chirp. The feedback path is configured to provide an input signal to the time to digital converter, and comprises modulation cancelling module operable to remove the frequency modulation resulting from the second control input from the output signal. The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input. The phase locked loop is operable in a chirp mode, in which the second control input is produced by determining a value for the second control input corresponding with a desired chirp frequency based on the stored second control input values in the memory, and in which the phase locked loop is configured to determine the first control input based on the feedback path from which the modulation cancelling module has removed the frequency modulation resulting from the second control input.
摘要翻译：公开了一种具有频率控制振荡器，反馈路径，时间到数字转换器和存储器的锁相环。频率控制振荡器包括用于改变频率控制振荡器的输出频率以跟踪参考频率的第一控制输入和用于调制输出信号的频率以产生啁啾的第二控制输入。反馈路径被配置为向时间到数字转换器提供输入信号，并且包括调制解除模块，其可操作以从输出信号中去除由第二控制输入产生的频率调制。存储器存储每个对应于期望啁啾频率并且补偿频率控制振荡器对第二控制输入的响应中的非线性的第二控制输入值。锁相环可以在啁啾模式下操作，其中通过基于存储器中存储的第二控制输入值确定与期望啁啾频率对应的第二控制输入的值来产生第二控制输入，其中，锁相环被配置为基于调制消除模块从其中移除由第二控制输入产生的频率调制的反馈路径来确定第一控制输入。

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