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1. 发明授权

US10242720B2 Dual sensing current latched sense amplifier 有权
公开(公告)号：US10242720B2
公开(公告)日：2019-03-26
申请号：US12731623
申请日：2010-03-25
申请人： Nan Chen , Ritu Chaba
发明人： Nan Chen , Ritu Chaba
IPC分类号： G11C7/00 , G11C7/06 , G11C7/08 , G11C7/12
摘要： A sense amplifier and method thereof are provided. The sense amplifier includes first and second transistors coupled to first and second bit lines, respectively. The first and second transistors are configured to connect the first and second bit lines to a differential amplifier during a first state (e.g., when a differential voltage is present on the first and second bit lines and prior to a sense signal transition) and to isolate the first and second bit lines from the differential amplifier during a second state (e.g., after the sense signal transition). The sense amplifier further includes a third transistor configured to deactivate the differential amplifier during the first state and configured to activate the differential amplifier during the second state.

2. 发明申请

US20110235449A1 Dual Sensing Current Latched Sense Amplifier 审中-公开
标题翻译：双感应电流锁定检测放大器
公开(公告)号：US20110235449A1
公开(公告)日：2011-09-29
申请号：US12731623
申请日：2010-03-25
申请人： Nan Chen , Ritu Chaba
发明人： Nan Chen , Ritu Chaba
IPC分类号： G11C7/06
CPC分类号： G11C7/00 , G11C7/065 , G11C7/08 , G11C7/12
摘要： A sense amplifier and method thereof are provided. The sense amplifier includes first and second transistors coupled to first and second bit lines, respectively. The first and second transistors are configured to connect the first and second bit lines to a differential amplifier during a first state (e.g., when a differential voltage is present on the first and second bit lines and prior to a sense signal transition) and to isolate the first and second bit lines from the differential amplifier during a second state (e.g., after the sense signal transition). The sense amplifier further includes a third transistor configured to deactivate the differential amplifier during the first state and configured to activate the differential amplifier during the second state.
摘要翻译：提供了一种读出放大器及其方法。读出放大器分别包括耦合到第一和第二位线的第一和第二晶体管。第一和第二晶体管被配置为在第一状态期间（例如，当差分电压存在于第一和第二位线上并且在感测信号转换之前）时将第一和第二位线连接到差分放大器并且隔离在第二状态（例如，在感测信号转换之后）来自差分放大器的第一和第二位线。读出放大器还包括第三晶体管，其被配置为在第一状态期间去激活差分放大器并且被配置为在第二状态期间激活差分放大器。

3. 发明授权

US07881137B2 Read assist for memory circuits with different precharge voltage levels for bit line pair 有权
标题翻译：对位线对具有不同预充电电压电平的存储电路的读辅助
公开(公告)号：US07881137B2
公开(公告)日：2011-02-01
申请号：US12256569
申请日：2008-10-23
申请人： Nan Chen , Ritu Chaba
发明人： Nan Chen , Ritu Chaba
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C7/12 , G11C11/417
摘要： A method increases stability of a memory circuit by pre-charging at least one bit line of the memory circuit to a first voltage, pre-charging at least one other bit line of the memory circuit to a second voltage, and equalizing charge across the bit lines so that the bit lines are pre-charged with a third voltage.
摘要翻译：一种方法通过将存储器电路的至少一个位线预充电到第一电压来增加存储器电路的稳定性，将存储器电路的至少一个其它位线预充电到第二电压，并且平衡位上的电荷使得位线被预充电第三电压。

4. 发明申请

US20100195366A1 Reducing Leakage Current in a Memory Device 有权
标题翻译：降低存储器件中的泄漏电流
公开(公告)号：US20100195366A1
公开(公告)日：2010-08-05
申请号：US12364105
申请日：2009-02-02
申请人： Nan Chen , Mehdi Hamidi Sani , Ritu Chaba
发明人： Nan Chen , Mehdi Hamidi Sani , Ritu Chaba
IPC分类号： G11C17/00 , G11C5/14 , G11C7/00
CPC分类号： G11C17/18 , G11C5/14 , G11C5/147 , G11C7/12
摘要： Memory devices and methods of reducing leakage current therein are disclosed. The memory device includes a memory core array including a plurality of bitlines, and peripheral logic configured to interface with the memory core array. The memory device further includes a footswitch configured to isolate the peripheral logic from a ground voltage, and a headswitch configured to isolate a precharge current path from the plurality of bit lines of the memory core array. Leakage current within the memory device may be reduced via the isolation provided by the footswitch and the headswitch.
摘要翻译：公开了减少漏电流的存储器件和方法。存储器件包括包括多个位线的存储器核心阵列和被配置为与存储器核心阵列接口的外围逻辑。存储器件还包括被配置为将外围逻辑与接地电压隔离的脚踏开关和被配置为将预充电电流路径与存储器核心阵列的多个位线隔离的头开关。通过脚踏开关和头开关提供的隔离可以减小存储器件内的泄漏电流。

5. 发明申请

US20100046276A1 Systems and Methods for Handling Negative Bias Temperature Instability Stress in Memory Bitcells 审中-公开
标题翻译：处理负偏压的系统和方法存储器位单元中的温度不稳定性应力
公开(公告)号：US20100046276A1
公开(公告)日：2010-02-25
申请号：US12194342
申请日：2008-08-19
申请人： Nan Chen , Cheng Zhong , Ritu Chaba
发明人： Nan Chen , Cheng Zhong , Ritu Chaba
IPC分类号： G11C11/00 , G11C5/14 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/04 , G11C7/20 , G11C7/22 , G11C11/413
摘要： A system and method reduce stress caused by NBTI effects by determining if a trigger event has occurred and if so inverting all input data values to the memory and all output data values from the memory during a period of time defined by the determined trigger event. In one embodiment, the trigger event is an alternate memory power-up.
摘要翻译：系统和方法通过确定触发事件是否已经发生，并且如果在所确定的触发事件所定义的时间段期间将所有输入数据值反转到存储器和所有输出数据值，从而减少由NBTI效应引起的应力。在一个实施例中，触发事件是备用存储器加电。

6. 发明授权

US09916904B2 Reducing leakage current in a memory device 有权
公开(公告)号：US09916904B2
公开(公告)日：2018-03-13
申请号：US12364105
申请日：2009-02-02
申请人： Nan Chen , Mehdi Hamidi Sani , Ritu Chaba
发明人： Nan Chen , Mehdi Hamidi Sani , Ritu Chaba
IPC分类号： G11C7/12 , G11C17/18 , G11C5/14
CPC分类号： G11C17/18 , G11C5/14 , G11C5/147 , G11C7/12
摘要： Memory devices and methods of reducing leakage current therein are disclosed. The memory device includes a memory core array including a plurality of bitlines, and peripheral logic configured to interface with the memory core array. The memory device further includes a footswitch configured to isolate the peripheral logic from a ground voltage, and a headswitch configured to isolate a precharge current path from the plurality of bit lines of the memory core array. Leakage current within the memory device may be reduced via the isolation provided by the footswitch and the headswitch.

7. 发明授权

US08223567B2 Memory read stability using selective precharge 有权
标题翻译：使用选择性预充电的存储器读稳定性
公开(公告)号：US08223567B2
公开(公告)日：2012-07-17
申请号：US12334817
申请日：2008-12-15
申请人： Mohamed H. Abu Rahma , Ritu Chaba , Nan Chen , Sei Seung Yoon
发明人： Mohamed H. Abu Rahma , Ritu Chaba , Nan Chen , Sei Seung Yoon
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C7/02 , G11C7/04 , G11C7/12 , G11C7/18 , G11C2207/002
摘要： A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell. A reduction in bit line voltage is achieved by precharging different sections of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between these sections. Read stability improves as a result of the reduction of bit line voltage. The relative capacitance difference between bit line sections determines the bit line voltage after charge sharing. Thus, the memory device is tolerant to process or temperature variations. The bit line voltage may be controlled in design by selecting the sections that are precharged to supply voltage or ground.
摘要翻译：存储器件利用选择性预充电和电荷共享以在访问位单元之前降低位线电压。通过将位线的不同部分预先充电到不同的电压（例如，电源电压和接地）并且使用这些部分之间的电荷共享来实现位线电压的降低。读取稳定性由于位线电压的降低而得到改善。位线部分之间的相对电容差确定电荷共享后的位线电压。因此，存储器件容忍处理或温度变化。可以通过选择预充电以供应电压或接地的部分来设计位线电压。

8. 发明申请

US20100103755A1 Read Assist for Memory Circuits 有权
标题翻译：读辅助内存电路
公开(公告)号：US20100103755A1
公开(公告)日：2010-04-29
申请号：US12256569
申请日：2008-10-23
申请人： Nan Chen , Ritu Chaba
发明人： Nan Chen , Ritu Chaba
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/419 , G11C7/12 , G11C11/417
摘要： A method increases stability of a memory circuit by pre-charging at least one bit line of the memory circuit to a first voltage, pre-charging at least one other bit line of the memory circuit to a second voltage, and equalizing charge across the bit lines so that the bit lines are pre-charged with a third voltage.
摘要翻译：一种方法通过将存储器电路的至少一个位线预充电到第一电压来增加存储器电路的稳定性，将存储器电路的至少一个其它位线预充电到第二电压，并且平衡位上的电荷使得位线被预充电第三电压。

9. 发明授权

US08183713B2 System and method of providing power using switching circuits 有权
标题翻译：使用开关电路提供电力的系统和方法
公开(公告)号：US08183713B2
公开(公告)日：2012-05-22
申请号：US11962195
申请日：2007-12-21
申请人： Hari Rao , Nan Chen , Ritu Chaba
发明人： Hari Rao , Nan Chen , Ritu Chaba
IPC分类号： H02J3/14
CPC分类号： H03K19/017581 , H03K19/00361 , Y10T307/438 , Y10T307/461
摘要： In a particular illustrative embodiment, a system is disclosed that includes a first power domain that is responsive to a first power switching circuit and a second power domain that is responsive to a second power switching circuit. The system also includes a logic circuit adapted to selectively activate the first power switching circuit and the second power switching circuit. At least one of the first power switching circuit and the second power switching circuit includes a first set of transistors adapted for activation during a first power up stage and a second set of transistors adapted for activation during a second power up stage after at least one of the first set of transistors are activated.
摘要翻译：在具体的说明性实施例中，公开了一种系统，其包括响应于第一功率开关电路的第一功率域和响应于第二功率开关电路的第二功率域。该系统还包括适于选择性地激活第一功率开关电路和第二功率开关电路的逻辑电路。第一功率开关电路和第二功率开关电路中的至少一个包括适于在第一加电阶段期间激活的第一组晶体管和适于在第二加电阶段中的第二组晶体管，其在至少一个第一组晶体管被激活。

10. 发明申请

US20090154274A1 Memory Read Stability Using Selective Precharge 有权
标题翻译：内存读取稳定性使用选择性预充电
公开(公告)号：US20090154274A1
公开(公告)日：2009-06-18
申请号：US12334817
申请日：2008-12-15
申请人： Mohamed R. Abu-Rahma , Ritu Chaba , Nan Chen , Sei Seung Yoon
发明人： Mohamed R. Abu-Rahma , Ritu Chaba , Nan Chen , Sei Seung Yoon
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C7/02 , G11C7/04 , G11C7/12 , G11C7/18 , G11C2207/002
摘要： A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell. A reduction in bit line voltage is achieved by precharging different sections of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between these sections. Read stability improves as a result of the reduction of bit line voltage. The relative capacitance difference between bit line sections determines the bit line voltage after charge sharing. Thus, the memory device is tolerant to process or temperature variations. The bit line voltage may be controlled in design by selecting the sections that are precharged to supply voltage or ground.
摘要翻译：存储器件利用选择性预充电和电荷共享以在访问位单元之前降低位线电压。通过将位线的不同部分预先充电到不同的电压（例如，电源电压和接地）并且使用这些部分之间的电荷共享来实现位线电压的降低。读取稳定性由于位线电压的降低而得到改善。位线部分之间的相对电容差确定电荷共享后的位线电压。因此，存储器件容忍处理或温度变化。可以通过选择预充电以供应电压或接地的部分来设计位线电压。

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