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1. 发明申请

US20140211895A1 Frequency Division 有权
标题翻译：频段
公开(公告)号：US20140211895A1
公开(公告)日：2014-07-31
申请号：US14236431
申请日：2012-08-02
申请人： Niko Mikkola , Petri Heliö , Paavo Väänänen
发明人： Niko Mikkola , Petri Heliö , Paavo Väänänen
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , H03K23/667 , H03K23/68
摘要： A frequency divider comprises a signal generation stage arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronisation stage is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.
摘要翻译：分频器包括信号产生级，被配置为以时钟频率采用时钟来提供第一参考信号和第二参考信号，第二参考信号对应于延迟了时钟信号的一半周期的第一参考信号。同步级被布置成通过在输出信号的每个周期一次切换第一参考信号和第二参考信号来产生具有从时钟频率划分的输出频率的输出信号。

2. 发明申请

US20130169327A1 Charge-to-Digital Timer 有权
标题翻译：电荷到数字定时器
公开(公告)号：US20130169327A1
公开(公告)日：2013-07-04
申请号：US13338390
申请日：2011-12-28
申请人： Petri Heliö , Petri Korpi , Niko Mikkola , Paavo Väänänen , Sami Vilhonen
发明人： Petri Heliö , Petri Korpi , Niko Mikkola , Paavo Väänänen , Sami Vilhonen
IPC分类号： H03L7/06 , H03M1/10 , H03M1/12
CPC分类号： H03L7/06 , G04F10/005 , G04F10/105
摘要： The charge-to-digital timer apparatus and method disclosed herein estimates the elapsed time between two signals, e.g., a start signal and a stop signal. To that end, at least a capacitive load is charged with a known current to generate a load voltage. Subsequently, a first voltage is ramped in a plurality of discrete voltage steps associated with a plurality of known capacitances until the ramped voltage satisfies a predetermined criterion relative to a second voltage. The elapsed time is determined from the discrete voltage steps, one of the first and second voltages, the known current, and the known capacitive load.
摘要翻译：这里公开的电荷数字计时装置和方法估计两个信号之间的经过时间，例如起始信号和停止信号。为此，至少电容性负载以已知电流充电以产生负载电压。随后，第一电压以与多个已知电容相关联的多个离散电压阶跃斜坡，直到斜坡电压相对于第二电压满足预定标准。经过的时间由离散的电压阶跃确定，第一和第二电压之一，已知电流和已知的容性负载。

3. 发明授权

US07764938B2 Signaling generation through multiplexing 有权
标题翻译：通过复用进行信令生成
公开(公告)号：US07764938B2
公开(公告)日：2010-07-27
申请号：US11707865
申请日：2007-02-20
申请人： Petri Heliö , Paavo Väänänen , Niko Mikkola , Jouni Kinnunen
发明人： Petri Heliö , Paavo Väänänen , Niko Mikkola , Jouni Kinnunen
IPC分类号： H04B1/06
CPC分类号： H03L7/18 , G06F1/08
摘要： The proposed apparatus and is used for signal generation by multiplexing signals such that there appears no glitches in an output signal. The present apparatus utilizes the knowledge of phase difference between input oscillator signals being multiplexed in order to provide a glitchless output signal. The apparatus comprises a first selection circuit configured to synchronize its response to a first control signal to a next determined event of one of input oscillator signals and convey an input oscillator signal to its output in response to the first control signal. The apparatus comprises a similar selection circuit for each input oscillator signal being multiplexed. Outputs of the selection circuits may be connected to a combining circuit which combines the outputs, thus providing the glitchless output signal.
摘要翻译：所提出的装置并且用于通过复用信号产生信号，使得在输出信号中没有毛刺。本装置利用被复用的输入振荡器信号之间的相位差的知识，以提供无毛刺输出信号。该装置包括第一选择电路，其被配置为将其响应与第一控制信号同步到输入振荡器信号之一的下一个确定的事件，并且响应于第一控制信号将输入振荡器信号传送到其输出。该装置包括被复用的每个输入振荡器信号的类似选择电路。选择电路的输出可以连接到组合输出的组合电路，从而提供无毛刺的输出信号。

4. 发明授权

US09485079B2 Frequency division 有权
标题翻译：分频
公开(公告)号：US09485079B2
公开(公告)日：2016-11-01
申请号：US14236431
申请日：2012-08-02
申请人： Niko Mikkola , Petri Heliö , Paavo Väänänen
发明人： Niko Mikkola , Petri Heliö , Paavo Väänänen
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00 , H04L7/00 , H03K23/66 , H03K23/68
CPC分类号： H04L7/0008 , H03K23/667 , H03K23/68
摘要： A frequency divider comprises a signal generation stage arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronization stage is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.
摘要翻译：分频器包括信号产生级，被配置为以时钟频率采用时钟来提供第一参考信号和第二参考信号，第二参考信号对应于延迟了时钟信号的一半周期的第一参考信号。同步级被布置成通过在输出信号的每个周期一次切换第一参考信号和第二参考信号来产生具有从时钟频率划分的输出频率的输出信号。

5. 发明授权

US08659360B2 Charge-to-digital timer 有权
标题翻译：电荷到数字定时器
公开(公告)号：US08659360B2
公开(公告)日：2014-02-25
申请号：US13338390
申请日：2011-12-28
申请人： Petri Heliö , Petri Korpi , Niko Mikkola , Paavo Väänänen , Sami Vilhonen
发明人： Petri Heliö , Petri Korpi , Niko Mikkola , Paavo Väänänen , Sami Vilhonen
IPC分类号： H03L7/085 , H03M1/50 , H03M1/56 , H03D13/00
CPC分类号： H03L7/06 , G04F10/005 , G04F10/105
摘要： The charge-to-digital timer apparatus and method disclosed herein estimates the elapsed time between two signals, e.g., a start signal and a stop signal. To that end, at least a capacitive load is charged with a known current to generate a load voltage. Subsequently, a first voltage is ramped in a plurality of discrete voltage steps associated with a plurality of known capacitances until the ramped voltage satisfies a predetermined criterion relative to a second voltage. The elapsed time is determined from the discrete voltage steps, one of the first and second voltages, the known current, and the known capacitive load.
摘要翻译：这里公开的电荷数字计时装置和方法估计两个信号之间的经过时间，例如起始信号和停止信号。为此，至少电容性负载以已知电流充电以产生负载电压。随后，第一电压以与多个已知电容相关联的多个离散电压阶跃斜坡，直到斜坡电压相对于第二电压满足预定标准。经过的时间由离散的电压阶跃确定，第一和第二电压之一，已知电流和已知的容性负载。

6. 发明申请

US20080070530A1 Signaling generation through multiplexing 有权
标题翻译：通过复用进行信令生成
公开(公告)号：US20080070530A1
公开(公告)日：2008-03-20
申请号：US11707865
申请日：2007-02-20
申请人： Petri Helio , Paavo Vaananen , Niko Mikkola , Jouni Kinnunen
发明人： Petri Helio , Paavo Vaananen , Niko Mikkola , Jouni Kinnunen
IPC分类号： H04B1/16
CPC分类号： H03L7/18 , G06F1/08
摘要： The proposed apparatus and is used for signal generation by multiplexing signals such that there appears no glitches in an output signal. The present apparatus utilizes the knowledge of phase difference between input oscillator signals being multiplexed in order to provide a glitchless output signal. The apparatus comprises a first selection circuit configured to synchronize its response to a first control signal to a next determined event of one of input oscillator signals and convey an input oscillator signal to its output in response to the first control signal. The apparatus comprises a similar selection circuit for each input oscillator signal being multiplexed. Outputs of the selection circuits may be connected to a combining circuit which combines the outputs, thus providing the glitchless output signal.
摘要翻译：所提出的装置并且用于通过复用信号产生信号，使得在输出信号中没有毛刺。本装置利用被复用的输入振荡器信号之间的相位差的知识，以提供无毛刺输出信号。该装置包括第一选择电路，其被配置为将其响应与第一控制信号同步到输入振荡器信号之一的下一个确定的事件，并且响应于第一控制信号将输入振荡器信号传送到其输出。该装置包括被复用的每个输入振荡器信号的类似选择电路。选择电路的输出可以连接到组合输出的组合电路，从而提供无毛刺的输出信号。

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