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1. 发明授权

US07724751B2 System for supporting communications among ATM devices, device for supporting data transmission, method for sending data, and computer program product 失效
标题翻译：用于支持ATM设备之间通信的系统，用于支持数据传输的设备，用于发送数据的方法和计算机程序产品
公开(公告)号：US07724751B2
公开(公告)日：2010-05-25
申请号：US11113107
申请日：2005-04-25
申请人： Norihisa Uchimoto , Koji Tatsumi , Kazuhisa Shimazaki , Koichiro Yamada , Satoshi Namura , Akio Morimoto , Michio Kusayanagi
发明人： Norihisa Uchimoto , Koji Tatsumi , Kazuhisa Shimazaki , Koichiro Yamada , Satoshi Namura , Akio Morimoto , Michio Kusayanagi
IPC分类号： H04L12/56
CPC分类号： H04L49/606 , H04L12/5601 , H04L2012/5625 , H04L2012/5665 , H04L2012/5674 , H04L2012/5679
摘要： A first communication device receives an ATM cell bound for a second ATM device from a first ATM device via an ATM interface, and then the first communication device sends a data frame including the ATM cell to the second ATM device via wide area Ethernet. In addition, the first communication device sends a synchronization frame to the second ATM device via the wide area Ethernet continuously at a predetermined time interval in accordance with a clock frequency of the first ATM device. A second communication device receives the synchronization frame and measures a clock frequency of the first ATM device in accordance with a time interval of receiving the synchronization frame so as to reproduce a clock having the same frequency as the measured clock frequency. After that, the second communication device sends the clock to the second ATM device via an ATM interface.
摘要翻译：第一通信设备经由ATM接口从第一ATM设备接收到用于第二ATM设备的ATM信元，然后第一通信设备经由广域以太网向第二ATM设备发送包括ATM信元的数据帧。此外，第一通信设备根据第一ATM设备的时钟频率，经由广域以太网连续地以预定时间间隔向第二ATM设备发送同步帧。第二通信设备接收同步帧，并根据接收到同步帧的时间间隔测量第一ATM设备的时钟频率，以再现具有与测量时钟频率相同频率的时钟。之后，第二通信设备经由ATM接口向第二ATM设备发送时钟。

2. 发明申请

US20060109849A1 System for supporting communications among ATM devices, device for supporting data transmission, method for sending data, and computer program product 失效
标题翻译：用于支持ATM设备之间通信的系统，用于支持数据传输的设备，用于发送数据的方法和计算机程序产品
公开(公告)号：US20060109849A1
公开(公告)日：2006-05-25
申请号：US11113107
申请日：2005-04-25
申请人： Norihisa Uchimoto , Koji Tatsumi , Kazuhisa Shimazaki , Koichiro Yamada , Satoshi Namura , Akio Morimoto , Michio Kusayanagi
发明人： Norihisa Uchimoto , Koji Tatsumi , Kazuhisa Shimazaki , Koichiro Yamada , Satoshi Namura , Akio Morimoto , Michio Kusayanagi
IPC分类号： H04L12/28
CPC分类号： H04L49/606 , H04L12/5601 , H04L2012/5625 , H04L2012/5665 , H04L2012/5674 , H04L2012/5679
摘要： A first communication device receives an ATM cell bound for a second ATM device from a first ATM device via an ATM interface, and then the first communication device sends a data frame including the ATM cell to the second ATM device via wide area Ethernet. In addition, the first communication device sends a synchronization frame to the second ATM device via the wide area Ethernet continuously at a predetermined time interval in accordance with a clock frequency of the first ATM device. A second communication device receives the synchronization frame and measures a clock frequency of the first ATM device in accordance with a time interval of receiving the synchronization frame so as to reproduce a clock having the same frequency as the measured clock frequency. After that, the second communication device sends the clock to the second ATM device via an ATM interface.
摘要翻译：第一通信设备经由ATM接口从第一ATM设备接收到用于第二ATM设备的ATM信元，然后第一通信设备经由广域以太网向第二ATM设备发送包括ATM信元的数据帧。此外，第一通信设备根据第一ATM设备的时钟频率，经由广域以太网连续地以预定时间间隔向第二ATM设备发送同步帧。第二通信设备接收同步帧，并根据接收到同步帧的时间间隔测量第一ATM设备的时钟频率，以再现具有与测量时钟频率相同频率的时钟。之后，第二通信设备经由ATM接口向第二ATM设备发送时钟。

3. 发明申请

US20090252169A1 SYSTEM FOR SUPPORTING COMMUNICATIONS AMONG ATM DEVICES, DEVICE FOR SUPPORTING DATA TRANSMISSION, METHOD FOR SENDING DATA, AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：用于支持ATM设备通信的系统，用于支持数据传输的设备，发送数据的方法和计算机程序产品
公开(公告)号：US20090252169A1
公开(公告)日：2009-10-08
申请号：US12482848
申请日：2009-06-11
申请人： Norihisa UCHIMOTO , Koji Tatsumi , Kazuhisa Shimazaki , Koichiro Yamada , Satoshi Namura , Akio Morimoto , Michio Kusayanagi
发明人： Norihisa UCHIMOTO , Koji Tatsumi , Kazuhisa Shimazaki , Koichiro Yamada , Satoshi Namura , Akio Morimoto , Michio Kusayanagi
IPC分类号： H04L12/56
CPC分类号： H04L49/606 , H04L12/5601 , H04L2012/5625 , H04L2012/5665 , H04L2012/5674 , H04L2012/5679
摘要： A first communication device receives an ATM cell bound for a second ATM device from a first ATM device via an ATM interface, and then the first communication device sends a data frame including the ATM cell to the second ATM device via wide area Ethernet. In addition, the first communication device sends a synchronization frame to the second ATM device via the wide area Ethernet continuously at a predetermined time interval in accordance with a clock frequency of the first ATM device. A second communication device receives the synchronization frame and measures a clock frequency of the first ATM device in accordance with a time interval of receiving the synchronization frame so as to reproduce a clock having the same frequency as the measured clock frequency. After that, the second communication device sends the clock to the second ATM device via an ATM interface.
摘要翻译：第一通信设备经由ATM接口从第一ATM设备接收到用于第二ATM设备的ATM信元，然后第一通信设备经由广域以太网向第二ATM设备发送包括ATM信元的数据帧。此外，第一通信设备根据第一ATM设备的时钟频率，经由广域以太网连续地以预定时间间隔向第二ATM设备发送同步帧。第二通信设备接收同步帧，并根据接收到同步帧的时间间隔测量第一ATM设备的时钟频率，以再现具有与测量时钟频率相同频率的时钟。之后，第二通信设备经由ATM接口向第二ATM设备发送时钟。

4. 发明申请

US20090041031A1 CONVERTER AND COMMUNICATION CONTROL METHOD 审中-公开
标题翻译：转换器和通信控制方法
公开(公告)号：US20090041031A1
公开(公告)日：2009-02-12
申请号：US12246655
申请日：2008-10-07
申请人： Shinya Nakagaki , Toshikazu Inoue , Kazuya Kumazaki , Mineharu Hattori , Tetsuji Ichikawa , Nobuo Iguchi , Akio Morimoto , Michio Kusayanagi
发明人： Shinya Nakagaki , Toshikazu Inoue , Kazuya Kumazaki , Mineharu Hattori , Tetsuji Ichikawa , Nobuo Iguchi , Akio Morimoto , Michio Kusayanagi
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L2012/5618 , H04L2012/5642 , H04L2012/5665 , H04L2012/5685
摘要： A converter for connecting its ATM network with other ATM networks through a LAN, which is provided with an address translation table storing external VPIs, internal VPIs uniquely assigned to the LAN, and opposing MAC addresses for opposing converters in correspondence and a processing unit for performing control for transmitting, to the LAN, frames changed from the external VPI/VCIs of headers of cells from its ATM network to the internal VPI/VCIs by referring to the address translation table and having opposing MAC addresses corresponding to the internal VPI/VCIs attached, removing the opposing MAC addresses of frames received from the LAN by referring to the address translation table, and transmitting cells changed from internal VPI/VCIs to external VPI/VCIs to its ATM network.
摘要翻译：一种用于通过LAN连接其ATM网络与其他ATM网络的转换器，其具有存储外部VPI的地址转换表，唯一地分配给该LAN的内部VPI以及对应的相对转换器的相对MAC地址以及用于执行用于通过参考地址转换表并且具有对应于附接的内部VPI / VCI的相对MAC地址将从ATM网络的小区的外部VPI / VCI从外部VPI / VCI发送到内部VPI / VCI的控制通过参考地址转换表去除从LAN接收到的帧的相对MAC地址，以及将从内部VPI / VCI改变到外部VPI / VCI的小区发送到其ATM网络。

5. 发明授权

US07599376B2 Converter and communication control method 失效
标题翻译：转换器和通讯控制方法
公开(公告)号：US07599376B2
公开(公告)日：2009-10-06
申请号：US11148753
申请日：2005-06-09
申请人： Shinya Nakagaki , Toshikazu Inoue , Kazuya Kumazaki , Mineharu Hattori , Tetsuji Ichikawa , Nobuo Iguchi , Akio Morimoto , Michio Kusayanagi
发明人： Shinya Nakagaki , Toshikazu Inoue , Kazuya Kumazaki , Mineharu Hattori , Tetsuji Ichikawa , Nobuo Iguchi , Akio Morimoto , Michio Kusayanagi
IPC分类号： H04L12/28
CPC分类号： H04L12/5601 , H04L2012/5618 , H04L2012/5642 , H04L2012/5665 , H04L2012/5685
摘要： A converter for connecting its ATM network with other ATM networks through a LAN, which is provided with an address translation table storing external VPIs, internal VPIs uniquely assigned to the LAN, and opposing MAC addresses for opposing converters in correspondence and a processing unit for performing control for transmitting, to the LAN, frames changed from the external VPI/VCIs of headers of cells from its ATM network to the internal VPI/VCIs by referring to the address translation table and having opposing MAC addresses corresponding to the internal VPI/VCIs attached, removing the opposing MAC addresses of frames received from the LAN by referring to the address translation table, and transmitting cells changed from internal VPI/VCIs to external VPI/VCIs to its ATM network.
摘要翻译：一种用于通过LAN连接其ATM网络与其他ATM网络的转换器，其具有存储外部VPI的地址转换表，唯一地分配给该LAN的内部VPI以及对应的相对转换器的相对MAC地址以及用于执行用于通过参考地址转换表并且具有对应于附接的内部VPI / VCI的相对MAC地址将从ATM网络的小区的外部VPI / VCI从外部VPI / VCI发送到内部VPI / VCI的控制通过参考地址转换表去除从LAN接收到的帧的相对MAC地址，以及将从内部VPI / VCI改变到外部VPI / VCI的小区发送到其ATM网络。

6. 发明申请

US20060182125A1 Converter and communication control method 失效
公开(公告)号：US20060182125A1
公开(公告)日：2006-08-17
申请号：US11148753
申请日：2005-06-09
申请人： Shinya Nakagaki , Toshikazu Inoue , Kazuya Kumazaki , Mineharu Hattori , Tetsuji Ichikawa , Nobuo Iguchi , Akio Morimoto , Michio Kusayanagi
发明人： Shinya Nakagaki , Toshikazu Inoue , Kazuya Kumazaki , Mineharu Hattori , Tetsuji Ichikawa , Nobuo Iguchi , Akio Morimoto , Michio Kusayanagi
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L12/5601 , H04L2012/5618 , H04L2012/5642 , H04L2012/5665 , H04L2012/5685
摘要： A converter for connecting its ATM network with other ATM networks through a LAN, which is provided with an address translation table storing external VPIs, internal VPIs uniquely assigned to the LAN, and opposing MAC addresses for opposing converters in correspondence and a processing unit for performing control for transmitting, to the LAN, frames changed from the external VPI/VCIs of headers of cells from its ATM network to the internal VPI/VCIs by referring to the address translation table and having opposing MAC addresses corresponding to the internal VPI/VCIs attached, removing the opposing MAC addresses of frames received from the LAN by referring to the address translation table, and transmitting cells changed from internal VPI/VCIs to external VPI/VCIs to its ATM network.

7. 发明授权

US07187658B2 Data transmission apparatus selecting efficient network or service class 失效
标题翻译：数据传输设备选择有效的网络或服务类
公开(公告)号：US07187658B2
公开(公告)日：2007-03-06
申请号：US09775975
申请日：2001-02-02
申请人： Hisako Koyanagi , Michio Kusayanagi , Jun Tanaka , Tomohiro Ishihara
发明人： Hisako Koyanagi , Michio Kusayanagi , Jun Tanaka , Tomohiro Ishihara
IPC分类号： H04L12/28 , H04L12/66 , G06F15/16
CPC分类号： H04L12/5692 , H04L29/06 , H04L45/00 , H04L45/302 , H04L45/54 , H04L69/22
摘要： A data transmission apparatus is provided for transmitting data received from a user terminal device through a plurality of networks to a destination, the user terminal device executing communication using an Internet protocol. The data transmission apparatus includes a routing table storing information relating a destination address of the data and addresses of the plurality of networks; an information table storing static and dynamic information about the plurality of networks; and a selection unit selecting one or the plurality of networks, through which the data transmission apparatus transmits the data to the destination, based on the static and dynamic information. The data transmission apparatus enables data transmission through the appropriate network by selecting the appropriate network based on the static and dynamic information about the plurality of networks.
摘要翻译：提供一种数据发送装置，用于通过多个网络将从用户终端装置接收的数据发送到目的地，所述用户终端装置使用因特网协议执行通信。数据发送装置包括存储与数据的目的地地址和多个网络的地址有关的信息的路由表; 存储关于所述多个网络的静态和动态信息的信息表; 以及选择单元，其基于静态和动态信息，选择一个或多个网络，数据发送设备通过该网络将数据发送到目的地。数据传输装置通过基于关于多个网络的静态和动态信息选择合适的网络，实现通过适当网络的数据传输。

8. 发明授权

US5892762A Buffer control system 失效
标题翻译：缓冲控制系统
公开(公告)号：US5892762A
公开(公告)日：1999-04-06
申请号：US651594
申请日：1996-05-22
申请人： Masato Okuda , Toshiyuki Sudo , Tomohiro Ishihara , Michio Kusayanagi
发明人： Masato Okuda , Toshiyuki Sudo , Tomohiro Ishihara , Michio Kusayanagi
IPC分类号： H04Q3/00 , H04L12/741 , H04L12/815 , H04L12/823 , H04L12/835 , H04L12/863 , H04L12/865 , H04L12/879 , H04J3/02
CPC分类号： H04L49/503 , H04L49/205 , H04L49/30 , H04L49/3081 , H04L49/90 , H04L2012/5651 , H04L2012/568 , H04L2012/5681 , H04L49/3009
摘要： A buffer control system is a system for implementing both a priority control process and a shaping process of cells with a hardware configuration of a small size in a network routing fixed-length packets which are respectively composed of transfer data and control information added to the transfer data, and to which priority information is assigned, according to the control information. If a cell written to an empty area of a cell buffer is a prioritized cell, and its expected output time is a time slot, an address where the cell is stored in the cell buffer is arranged in a time slot in a prioritized cell entry memory. When it reaches the time to read the cell stored in the time slot, the address stored in the time slot is written to an output list chain, and the cell is read from that address. The empty area of the buffer is managed using a free list chain.
摘要翻译：缓冲器控制系统是在网络路由固定长度分组中实现具有小尺寸的硬件配置的小区的优先级控制处理和整形处理的系统，其分别由传送数据和添加到传送的控制信息组成数据，并根据控制信息分配给哪个优先级信息。如果写入单元缓冲器的空区域的单元是优先化单元，并且其预期输出时间是时隙，则将单元存储在单元缓冲器中的地址排列在优先小区输入存储器中的时隙中。当达到读取存储在时隙中的单元的时间时，将时隙中存储的地址写入输出列表链，并从该地址读取单元。缓冲区的空白区域使用免费的列表链条进行管理。

9. 发明授权

US5335222A Traffic control system for asynchronous transfer mode exchange 失效
标题翻译：用于异步传输模式交换的交通控制系统
公开(公告)号：US5335222A
公开(公告)日：1994-08-02
申请号：US076793
申请日：1993-06-15
申请人： Jyoei Kamoi , Hichiro Hayami , Yuji Kato , Toshio Shimoe , Shunji Abe , Michio Kusayanagi , Haruo Mukai , Toshio Soumiya
发明人： Jyoei Kamoi , Hichiro Hayami , Yuji Kato , Toshio Shimoe , Shunji Abe , Michio Kusayanagi , Haruo Mukai , Toshio Soumiya
IPC分类号： H04L12/56 , H04Q11/04 , H04J3/14
CPC分类号： H04L12/5601 , H04L12/5602 , H04L49/106 , H04L49/203 , H04L49/255 , H04Q11/0478 , H04L2012/5629 , H04L2012/5634 , H04L2012/5647 , H04L2012/5649 , H04L2012/5651 , H04L2012/5672 , H04L2012/5681 , H04L2012/5682 , H04L2012/5684
摘要： A call admission control system in an asynchronous transfer mode exchange includes a unit for describing attribute parameters of a cell from the subscriber terminal; a unit for calculating, based on the attribute parameters, the average and the dispersion of the traffic speeds of the call; a unit for managing data of the average and the dispersion on each output route and data relating to each subscriber; and a unit for calculating the total average and the total dispersion of the data speeds on the selection output route; and a unit for calculating prediction values of cell abandon rate and end-to-end delay based on the average and the dispersion on the selected output route calculated by the total average and dispersion calculating unit, and for comparing the prediction values with the required service quality of cell discard rate and end-to end delay, for determining whether or not the requesting call may be connected.
摘要翻译：异步传输模式交换中的呼叫准入控制系统包括用于从用户终端描述小区的属性参数的单元; 基于属性参数计算呼叫的通信速度的平均值和离散度的单元; 用于管理每个输出路线上的平均值和色散数据的单元以及与每个用户有关的数据; 以及用于计算选择输出路线上的数据速度的总平均和总色散的单元; 以及用于基于由总平均和色散计算单元计算的所选择的输出路线上的平均值和色散来计算单元放弃率和端对端延迟的预测值的单元，并且用于将预测值与所需服务进行比较用于确定请求呼叫是否可以被连接的小区丢弃率和端到端延迟的质量。

10. 发明授权

US07359389B2 Packet switch for interfacing between LAN and WAN 有权
标题翻译：分组交换机用于LAN和WAN之间的接口
公开(公告)号：US07359389B2
公开(公告)日：2008-04-15
申请号：US10116274
申请日：2002-04-04
申请人： Michio Kusayanagi
发明人： Michio Kusayanagi
IPC分类号： H04L12/56
CPC分类号： H04L12/2898 , H04L12/2856 , H04L45/742 , H04L49/201 , H04L49/351
摘要： A packet switch interfacing between a WAN and a LAN accommodating a terminal includes an address table storing a relation between an address of the terminal and an input port receiving a packet transmitted from the terminal, and an address learning unit for storing in the address table the relation between the source address of the received packet and the input port receiving the received packet. Further the packet switch includes a SW unit for effecting control to transmit the received packet according to whether or not stored in the address table, and then transmit the received packet to the WAN when a packet having a source address identical with the destination address of the received packet has not been received from the LAN.
摘要翻译： WAN与容纳终端的LAN之间的分组交换机接口包括存储终端的地址和接收从终端发送的分组的输入端口之间的关系的地址表，以及地址学习单元，用于在地址表中存储接收到的分组的源地址与接收到的分组的输入端口之间的关系。此外，分组交换机包括SW单元，用于根据是否存储在地址表中进行控制以发送接收到的分组，然后当具有与源地址的目的地址相同的源地址的分组时，将接收到的分组发送到WAN 接收到的数据包尚未从LAN接收到。

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