专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08861362B2 Data flow control 有权
标题翻译：数据流控制
公开(公告)号：US08861362B2
公开(公告)日：2014-10-14
申请号：US14152658
申请日：2014-01-10
申请人： GOS Networks Ltd
发明人： Neil James Davies , Peter William Thompson , Judith Yvonne Holyer , Christopher James Vowden , Laura Anne Lafave , Graham Willmott
IPC分类号： G06F11/00 , H04L1/00 , H04L12/26 , H04Q11/04 , H04L12/851 , H04L12/70
CPC分类号： H04L47/2433 , H04L2012/5651 , H04L2012/5679 , H04L2012/568 , H04L2012/5682 , H04L2012/5684 , H04Q11/0478
摘要： One aspect provides a method of controlling an information flow in a data transmission system. In one embodiment, the method comprises receiving a plurality of data packets and generating a modified information flow. Data packets in the modified information flow are spaced with a variable spacing whilst the order of the data packets is maintained. The variable spacing between the data packets is exponentially distributed.
摘要翻译：一方面提供一种控制数据传输系统中的信息流的方法。在一个实施例中，该方法包括接收多个数据分组并生成修改的信息流。修改的信息流中的数据分组以可变间隔间隔，同时保持数据分组的顺序。数据包之间的可变间距是指数分布的。

2. 再颁专利

USRE42092E1 Integrated circuit that processes communication packets with a buffer management engine having a pointer cache 有权
标题翻译：用具有指针高速缓冲存储器的缓冲器管理引擎来处理通信包的集成电路
公开(公告)号：USRE42092E1
公开(公告)日：2011-02-01
申请号：US12122625
申请日：2008-05-16
申请人： Joseph B. Tompkins , Daniel J. Lussier , Wilson P. Snyder, II
发明人： Joseph B. Tompkins , Daniel J. Lussier , Wilson P. Snyder, II
IPC分类号： H04L12/28 , G06F13/00
CPC分类号： H04L12/5602 , H04L47/2425 , H04L47/50 , H04L47/6215 , H04L49/3081 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9073 , H04L49/9078 , H04L49/9094 , H04L2012/5651 , H04L2012/5679 , H04L2012/5684 , H04Q11/0478
摘要： An integrated circuit processes communication packets and comprises a pointer cache and control logic. The pointer cache store pointers that correspond to external buffers that are external to the integrated circuit and configured to store the communication packets. The control logic allocates the external buffers as the corresponding pointers are read from the pointer cache and de-allocates the external buffers as the corresponding pointers are written back to the pointer cache.
摘要翻译：集成电路处理通信分组并且包括指针高速缓存和控制逻辑。指针缓存存储指针，其对应于集成电路外部并被配置为存储通信分组的外部缓冲器。当相应的指针从指针高速缓存中读取时，控制逻辑分配外部缓冲区，并将相应的指针写回指针高速缓存中，并分配外部缓冲区。

3. 发明申请

US20100202290A1 Data Flow Control 有权
标题翻译：数据流控制
公开(公告)号：US20100202290A1
公开(公告)日：2010-08-12
申请号：US12711932
申请日：2010-02-24
申请人： Neil James Davies , Judith Yvonne Holyer , Laura Anne Lafave , Peter William Thompson , Christopher James Vowden , Graham Willmott
发明人： Neil James Davies , Judith Yvonne Holyer , Laura Anne Lafave , Peter William Thompson , Christopher James Vowden , Graham Willmott
IPC分类号： H04L12/26 , H04L12/56
CPC分类号： H04L47/2433 , H04L2012/5651 , H04L2012/5679 , H04L2012/568 , H04L2012/5682 , H04L2012/5684 , H04Q11/0478
摘要： There is disclosed a method and controller for controlling an information flow in a data transmission system. In one embodiment, the method and controller receives a plurality of data packets. The method and controller further generate a modified information flow by providing a variable spacing between the data packets that is exponentially distributed. The variable spacing between the data packets may be random or pseudo-random.
摘要翻译：公开了一种用于控制数据传输系统中的信息流的方法和控制器。在一个实施例中，方法和控制器接收多个数据分组。方法和控制器通过在指数分布的数据分组之间提供可变间隔来进一步产生修改的信息流。数据分组之间的可变间隔可以是随机的或伪随机的。

4. 发明授权

US07339942B2 Dynamic queue allocation and de-allocation 有权
标题翻译：动态队列分配和取消分配
公开(公告)号：US07339942B2
公开(公告)日：2008-03-04
申请号：US10264786
申请日：2002-10-04
申请人： David Lynn Morgan , Stephen Clawson , James Freeman
发明人： David Lynn Morgan , Stephen Clawson , James Freeman
IPC分类号： H04L12/28 , H04J3/16
CPC分类号： H04L47/20 , H04L12/4625 , H04L41/0893 , H04L47/10 , H04L47/2408 , H04L47/2441 , H04L47/245 , H04L47/76 , H04L47/781 , H04L47/805 , H04L47/822 , H04L49/205 , H04L49/254 , H04L49/30 , H04L49/3027 , H04L49/90 , H04L2012/5625 , H04L2012/5678 , H04L2012/5684 , H04Q11/0478
摘要： A dynamic queue allocation and de-allocation mechanism for managing traffic flowing through a switching node. If a packet matches conditions of a particular QoS policy rule, a determination is made as to whether a queue associated with the matched QoS policy rule exists on an egress port that is to forward the packet. If such a queue does not exist, a determination is made as to whether enough resources are available for dynamically creating the queue according to the QoS action parameters of the matched QoS policy rule. If the new queue may not be created because of resource limitation, queues of lower priority existing on the port are reclaimed and their resources reassigned to the new queue.
摘要翻译：用于管理流经交换节点的流量的动态队列分配和去分配机制。如果分组匹配特定QoS策略规则的条件，则确定与要匹配的QoS策略规则相关联的队列是否存在于要转发分组的出口端口上。如果不存在这样的队列，则根据匹配的QoS策略规则的QoS动作参数确定足够的资源是否可用于动态创建队列。如果由于资源限制而不能创建新的队列，那么回收端口上优先级较低的队列被重新分配，并将其资源重新分配给新队列。

5. 发明申请

US20050152272A1 Data networks 有权
标题翻译：数据网络
公开(公告)号：US20050152272A1
公开(公告)日：2005-07-14
申请号：US10870444
申请日：2004-06-18
申请人： Nils Bjoerkman , Simon Crosby , Alexander Latour-Henner , Ian Leslie , John Lewis , Fergal Toomey , Raymond Russell
发明人： Nils Bjoerkman , Simon Crosby , Alexander Latour-Henner , Ian Leslie , John Lewis , Fergal Toomey , Raymond Russell
IPC分类号： H04L12/54 , H04L12/70 , H04L12/947 , H04Q11/04 , H04L12/26
CPC分类号： H04L12/5602 , H04L49/256 , H04L2012/5632 , H04L2012/5684 , H04Q11/0478
摘要： A data network in which at least one switch is provided with the facility for estimating current network demands using a polygonal approximation to scaled cumulant generating function. The approximation is iteratively refined in accordance with sampled data passing through the switch. The switch estimates the demand associated with a new data processing request as it is received by the switch and decides whether to accept the request based on available resources.
摘要翻译：一种数据网络，其中至少一个开关具有用于使用对缩放的累积量产生函数的多边形近似来估计当前网络需求的设施。根据通过开关的采样数据，迭代地改进近似值。交换机估计与交换机接收到的新数据处理请求相关联的需求，并根据可用资源决定是否接受请求。

6. 发明申请

US20050100009A1 Method and system for bandwidth estimation 有权
标题翻译：带宽估计的方法和系统
公开(公告)号：US20050100009A1
公开(公告)日：2005-05-12
申请号：US10650032
申请日：2003-08-28
申请人： Dmitri Botvich
发明人： Dmitri Botvich
IPC分类号： H04J3/16 , H04L12/24 , H04L12/70 , H04L12/801 , H04L12/851 , H04Q11/04 , H04L12/56
CPC分类号： H04L43/0882 , H04L41/0896 , H04L41/5003 , H04L47/10 , H04L47/11 , H04L47/2441 , H04L2012/5632 , H04L2012/5684 , H04L2012/5686 , H04Q11/0478
摘要： The invention relates to a system and method for estimating the effective bandwidth on-line at a node in a communications network. The invention works by measuring the effective bandwidth and the mean rate of traffic flow for an identified type of traffic flow off-line, defining a relationship between the two measured values and storing the relationship in a database of relationships for different identifiable types of traffic flow off-line. A type of traffic flow or group of flows is identified on-line from which the mean rate of traffic flow is measured on-line which is a relatively simple measurement to make. From the database of relationships a relationship is obtained from which the effective bandwidth is estimated for the traffic flow or flows on-line. This is the simplest operation of the invention. The invention further discloses means for incorporating loss ratio and delays in the estimation of the effective bandwidth on-line.
摘要翻译：本发明涉及一种用于在通信网络中的节点处在线估计有效带宽的系统和方法。本发明通过测量离线的已识别类型的业务流的有效带宽和平均通信速率来定义两个测量值之间的关系并将关系存储在关于不同可识别类型的业务流的关系数据库中离线。在线确定一种类型的交通流量或一组流量，在该线路上，在线测量交通流量的平均速率，这是进行相对简单的测量。从关系数据库中获得关于业务流量估计有效带宽或在线流量的关系。这是本发明的最简单的操作。本发明还公开了在线有效带宽的估计中包含丢失率和延迟的装置。

7. 发明授权

US06879562B2 Validation of call processing network performance 失效
标题翻译：呼叫处理网络性能验证
公开(公告)号：US06879562B2
公开(公告)日：2005-04-12
申请号：US10441618
申请日：2003-05-20
申请人： Ralph L. Hoefelmeyer , Michael L. Hutchinson
发明人： Ralph L. Hoefelmeyer , Michael L. Hutchinson
IPC分类号： H04L12/46 , H04L12/56 , G01R31/08
CPC分类号： H04L49/602 , H04L12/4604 , H04L49/20 , H04L49/253 , H04L49/352 , H04L49/555 , H04L2012/5667 , H04L2012/5684
摘要： A call processing network performance verification and validation system and test methodology. The call processing network implements Internet Protocol (IP) subnet topology, ATM WAN configuration, equipment placement, and device configuration to provide partitioning of a call processing application across multiple sites. The partitioning reduces latency for mission critical messages, while providing for necessary provisioning traffic needs. Further, the overall topology provides the redundancy and resiliency necessary for mission critical call processing application, utilizing the IP subnets, ATM permanent virtual circuits, network device configuration, and server segregation to achieve Quality of Service (QoS). The validation testing method and system proves out the various segregated routes, verifies subnet integrity and measures total latency and data path traversal in a verifiable manner.
摘要翻译：呼叫处理网络性能验证和验证系统和测试方法。呼叫处理网络实现互联网协议（IP）子网拓扑，ATM WAN配置，设备布置和设备配置，以提供跨多个站点的呼叫处理应用程序的分区。分区可以减少任务关键消息的延迟，同时提供必要的配置流量需求。此外，整体拓扑提供了任务关键呼叫处理应用所需的冗余和弹性，利用IP子网，ATM永久虚拟电路，网络设备配置和服务器隔离来实现服务质量（QoS）。验证测试方法和系统证明了各种隔离路由，验证子网完整性，并以可验证的方式测量总延迟和数据路径遍历。

8. 发明授权

US06804239B1 Integrated circuit that processes communication packets with co-processor circuitry to correlate a packet stream with context information 有权
标题翻译：用协处理器电路处理通信分组以将分组流与上下文信息相关联的集成电路
公开(公告)号：US06804239B1
公开(公告)日：2004-10-12
申请号：US09640231
申请日：2000-08-16
申请人： Daniel J. Lussier , Joseph B. Tompkins , Wilson P. Snyder II
发明人： Daniel J. Lussier , Joseph B. Tompkins , Wilson P. Snyder II
IPC分类号： H04L1228
CPC分类号： H04L12/5602 , H04L47/2425 , H04L47/50 , H04L47/6215 , H04L49/3081 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9073 , H04L49/9078 , H04L49/9094 , H04L2012/5651 , H04L2012/5679 , H04L2012/5684 , H04Q11/0478
摘要： An integrated circuit comprises co-processor circuitry and a core processor. The co-processor circuitry comprises context buffers and data buffers. The co-processor circuitry receives and stores one of the communication packets in one of the data buffers. The co-processor circuitry correlates the one communication packet with one of a plurality of channel descriptors. The co-processor circuitry associates the one data buffer with one of the context buffers holding the one channel descriptor to maintain the correlation between the one communication packet and the one channel descriptor. The co-processor circuitry prevents multiple valid copies of the one channel descriptor from existing in the context buffers. In some examples of the invention, this is accomplished by tracking a number of the data buffers associated with the one context buffer. The core processor executes a packet processing software application that directs the processor to process the one communication packet in the one data buffer based on the one channel descriptor in the one context buffer.
摘要翻译：集成电路包括协处理器电路和核心处理器。协处理器电路包括上下文缓冲器和数据缓冲器。协处理器电路在一个数据缓冲器中接收并存储一个通信分组。协处理器电路将一个通信分组与多个信道描述符之一相关联。协处理器电路将一个数据缓冲器与保持一个通道描述符的上下文缓冲器之一相关联，以维持一个通信分组与一个通道描述符之间的相关性。协处理器电路防止在上下文缓冲器中存在的一个通道描述符的多个有效副本。在本发明的一些示例中，这通过跟踪与一个上下文缓冲器相关联的数个数据缓冲器来实现。核心处理器执行分组处理软件应用，其指导处理器基于一个上下文缓冲器中的一个信道描述符处理一个数据缓冲器中的一个通信分组。

9. 发明授权

US06801518B2 High speed cross point switch routing circuit with word-synchronous serial back plane 失效
公开(公告)号：US06801518B2
公开(公告)日：2004-10-05
申请号：US10074106
申请日：2002-02-12
申请人： John P. Mullaney , Gary M. Lee
发明人： John P. Mullaney , Gary M. Lee
IPC分类号： H04L1250
CPC分类号： H04L12/5601 , H04J3/0685 , H04L7/04 , H04L49/1576 , H04L49/3081 , H04L2012/5652 , H04L2012/5674 , H04L2012/5679 , H04L2012/5681 , H04L2012/5684 , H04Q11/0478
摘要： An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock. The switch circuit compares the boundary of the received word clock to the master word clock and, if misaligned, the transceiver shifts its transmitted word by one bit and retries. Necessary edge transition density is provided by overhead bits which also designate special command words asserted between a transceiver and a switch circuit. Flow control information is routed from a receiving transceiver back to the transmitting transceiver using the overhead bits in order to assert a ready-to-receive or a not-ready-to-receive flow control signal. The overhead bits additionally provide information regarding connection requests and other information.

10. 发明授权

US06760337B1 Integrated circuit that processes communication packets with scheduler circuitry having multiple priority levels 有权
标题翻译：用具有多个优先级的调度器电路处理通信分组的集成电路
公开(公告)号：US06760337B1
公开(公告)日：2004-07-06
申请号：US09639966
申请日：2000-08-16
申请人： Wilson P. Snyder, II , Joseph B. Tompkins , Daniel J. Lussier
发明人： Wilson P. Snyder, II , Joseph B. Tompkins , Daniel J. Lussier
IPC分类号： H04L1256
CPC分类号： H04L12/5602 , H04L47/2425 , H04L47/50 , H04L47/6215 , H04L49/3081 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9073 , H04L49/9078 , H04L49/9094 , H04L2012/5651 , H04L2012/5679 , H04L2012/5684 , H04Q11/0478
摘要： An integrated circuit processes communication packets and comprises a core processor and scheduling circuitry. The core processor executes a software application that directs the core processor to process the communication packets. The scheduling circuitry comprises multiple scheduling boards where at least some of the scheduling boards have multiple priority levels. The scheduling circuitry processes the scheduling boards to schedule and subsequently initiate transmission of the communication packets.
摘要翻译：集成电路处理通信分组并且包括核心处理器和调度电路。核心处理器执行指导核心处理器处理通信数据包的软件应用程序。调度电路包括多个调度板，其中至少一些调度板具有多个优先级。调度电路处理调度板以调度并随后发起通信分组的传输。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式