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1. 发明授权

US07605612B1 Techniques for reducing power requirements of an integrated circuit 失效
标题翻译：降低集成电路功耗要求的技术
公开(公告)号：US07605612B1
公开(公告)日：2009-10-20
申请号：US12121827
申请日：2008-05-16
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Daniel L. Stasiak , Albert J. Van Norstrand, Jr.
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Daniel L. Stasiak , Albert J. Van Norstrand, Jr.
IPC分类号： H03K19/00
CPC分类号： H03K19/0016 , G06F1/3203 , G06F1/3237 , G06F17/505 , G06F2217/78 , G06F2217/84 , Y02D10/128
摘要： A technique for clock gating a clock domain of an integrated circuit includes storing first, second, and third values in a control register. The first value corresponds to a first number of clock cycles to wait before initiating clock gating, the second value corresponds to a second number of clock cycles in which clock gating is performed, and the third value corresponds to a third number of clock cycles in which clock gating is not performed. One of the first, second, and third values is selectively loaded from the control register into a counting circuit. The counting circuit counts from the loaded one of the first, second, and third values to a transition value. A compare signal is received at the control state machine (from the counting circuit) that indicates the counting circuit has reached the transition value. Based on a current state of the control state machine, a load signal is provided to the counting circuit to cause the counting circuit to load an associated one of the first, second, and third values from the control register.
摘要翻译：时钟选通集成电路的时钟域的技术包括将第一，第二和第三值存储在控制寄存器中。第一值对应于在启动时钟门控之前等待的第一数量的时钟周期，第二值对应于执行时钟门控的第二数量的时钟周期，并且第三值对应于第三数量的时钟周期，其中不执行时钟门控。第一，第二和第三值之一被选择性地从控制寄存器加载到计数电路中。计数电路从加载的第一，第二和第三值之一计数到转换值。在控制状态机（从计数电路）接收到比较信号，指示计数电路已经达到转换值。基于控制状态机的当前状态，向计数电路提供负载信号，使得计数电路从控制寄存器加载相关的第一，第二和第三值中的一个。

2. 发明授权

US07633316B2 Transmission gate multiplexer 失效
标题翻译：传输门复用器
公开(公告)号：US07633316B2
公开(公告)日：2009-12-15
申请号：US12256582
申请日：2008-10-23
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/002
摘要： A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术包括从多个传输门组选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

3. 发明申请

US20090072863A1 Transmission Gate Multiplexer 失效
标题翻译：传输门复用器
公开(公告)号：US20090072863A1
公开(公告)日：2009-03-19
申请号：US12256582
申请日：2008-10-23
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20 , G06F9/305
CPC分类号： H03K17/002
摘要： A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术包括从多个传输门组选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

4. 发明申请

US20080303553A1 METHOD AND APPARATUS FOR A CONFIGURABLE LOW POWER HIGH FAN-IN MULTIPLEXER 有权
标题翻译：一种可配置低功率高风扇多路复用器的方法和装置
公开(公告)号：US20080303553A1
公开(公告)日：2008-12-11
申请号：US11759426
申请日：2007-06-07
申请人： OWEN CHIANG , Christopher M. Durham , Peter J. Klim , James D. Warnock
发明人： OWEN CHIANG , Christopher M. Durham , Peter J. Klim , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K19/0008 , H03K17/005
摘要： A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.
摘要翻译：公开了一种可配置的低功率高风扇多路复用器（MUX）。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。每个电流控制元件接收对应于数据信号的数据信号和选择信号。如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使得相应的数据信号能够提供输入到与MUX的输出耦合的逻辑门（例如，NAND门）。如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

5. 发明授权

US07693701B2 Structure for a configurable low power high fan-in multiplexer 失效
标题翻译：可配置低功耗高风扇多路复用器的结构
公开(公告)号：US07693701B2
公开(公告)日：2010-04-06
申请号：US12132501
申请日：2008-06-03
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
IPC分类号： G06F17/50 , H03K19/094
CPC分类号： H03K17/005 , H03K19/0008
摘要： A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.
摘要翻译：公开了一种可配置的低功率高扇入多路复用器（MUX）及其设计结构。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。每个电流控制元件接收对应于数据信号的数据信号和选择信号。如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使相应的数据信号能够提供输入到与MUX的输出耦合的逻辑门（例如，NAND门）。如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

6. 发明授权

US07466164B1 Method and apparatus for a configurable low power high fan-in multiplexer 有权
标题翻译：用于可配置低功率高风扇多路复用器的方法和装置
公开(公告)号：US07466164B1
公开(公告)日：2008-12-16
申请号：US11759426
申请日：2007-06-07
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
IPC分类号： H03K19/94
CPC分类号： H03K19/0008 , H03K17/005
摘要： A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.
摘要翻译：公开了一种可配置的低功率高风扇多路复用器（MUX）。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。每个电流控制元件接收对应于数据信号的数据信号和选择信号。如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使相应的数据信号能够提供输入到与MUX的输出耦合的逻辑门（例如，NAND门）。如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

7. 发明申请

US20080303554A1 STRUCTURE FOR A CONFIGURABLE LOW POWER HIGH FAN-IN MULTIPLEXER 失效
标题翻译：可配置低功率高风扇多路复用器的结构
公开(公告)号：US20080303554A1
公开(公告)日：2008-12-11
申请号：US12132501
申请日：2008-06-03
申请人： Owen CHIANG , Christopher M. Durham , Peter J. Klim , James D. Warnock
发明人： Owen CHIANG , Christopher M. Durham , Peter J. Klim , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/005 , H03K19/0008
摘要： A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.
摘要翻译：公开了一种可配置的低功率高扇入多路复用器（MUX）及其设计结构。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。每个电流控制元件接收对应于数据信号的数据信号和选择信号。如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使相应的数据信号能够提供输入到与MUX的输出耦合的逻辑门（例如，NAND门）。如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

8. 发明申请

US20090096486A1 Structure for Transmission Gate Multiplexer 审中-公开
标题翻译：传输门复用器的结构
公开(公告)号：US20090096486A1
公开(公告)日：2009-04-16
申请号：US12028940
申请日：2008-02-11
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/005
摘要： A technique and design structure for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术和设计结构包括从多个传输门组中选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

9. 发明授权

US07466165B1 Transmission gate multiplexer 失效
标题翻译：传输门复用器
公开(公告)号：US07466165B1
公开(公告)日：2008-12-16
申请号：US11854604
申请日：2007-09-13
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/002
摘要： A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术包括从多个传输门组选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

10. 发明申请

US20120262197A1 TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES 有权
公开(公告)号：US20120262197A1
公开(公告)日：2012-10-18
申请号：US13533191
申请日：2012-06-26
申请人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
发明人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
IPC分类号： G01R31/3187 , G01R1/067 , G01R31/00 , G01R31/02
CPC分类号： H01L22/32 , H01L21/4846 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/6835 , H01L2224/13005 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079
摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

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