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1. 发明授权

US07906420B2 Method and apparatus for forming planar alloy deposits on a substrate 有权
标题翻译：在基板上形成平面合金沉积物的方法和装置
公开(公告)号：US07906420B2
公开(公告)日：2011-03-15
申请号：US12627249
申请日：2009-11-30
申请人： Peter Alfred Gruber , Paul Alfred Lauro , Jae-Woong Nah
发明人： Peter Alfred Gruber , Paul Alfred Lauro , Jae-Woong Nah
IPC分类号： H01L21/44
CPC分类号： B23K1/0016 , H01L21/4853 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/0554 , H01L2224/05567 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/1183 , H01L2224/1184 , H01L2224/11848 , H01L2224/13099 , H01L2224/16225 , H01L2224/81192 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , Y10T428/24612 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method for forming alloy deposits at selected areas on a receiving substrate includes the steps of: providing an alloy carrier including at least a first decal including a first plurality of openings and a second decal including a second plurality of openings, the first and second decals being arranged such that each of the first plurality of openings is in alignment with a corresponding one of the second plurality of openings; filling the first and second plurality of openings with molten alloy; cooling the molten alloy to thereby form at least first and second plugs, the first plug having a first surface and a second surface substantially parallel to one another, the second plug having a third surface and a fourth surface substantially parallel to one another; removing at least one of the first and second decals to at least partially expose the first and second plugs; aligning the alloy carrier with the receiving substrate so that the first and second plugs correspond to the selected areas on the receiving substrate; and transferring the first plug to a first of the selected areas and the second plug to a second of the selected areas.
摘要翻译：一种用于在接收基板上的选定区域形成合金沉积物的方法包括以下步骤：提供合金载体，其包括至少包括第一多个开口的第一贴花和包括第二多个开口的第二贴花，第一和第二贴花被布置成使得所述第一多个开口中的每一个与所述第二多个开口中的对应的一个开口对准; 用熔融合金填充第一和第二多个开口; 冷却所述熔融合金，从而形成至少第一和第二塞子，所述第一塞子具有基本上彼此平行的第一表面和第二表面，所述第二塞子具有基本上彼此平行的第三表面和第四表面; 去除所述第一和第二贴花中的至少一个以至少部分地暴露所述第一和第二插塞; 将合金载体与接收基板对准，使得第一和第二插塞对应于接收基板上的选定区域; 以及将所述第一插头转移到所选择的区域中的第一个，并且将所述第二插头转移到所选择的区域中的第二个。

2. 发明授权

US07867842B2 Method and apparatus for forming planar alloy deposits on a substrate 有权
公开(公告)号：US07867842B2
公开(公告)日：2011-01-11
申请号：US12181852
申请日：2008-07-29
申请人： Peter Alfred Gruber , Paul Alfred Lauro , Jae-Woong Nah
发明人： Peter Alfred Gruber , Paul Alfred Lauro , Jae-Woong Nah
IPC分类号： H01L21/8242
CPC分类号： B23K1/0016 , H01L21/4853 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/0554 , H01L2224/05567 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/1183 , H01L2224/1184 , H01L2224/11848 , H01L2224/13099 , H01L2224/16225 , H01L2224/81192 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , Y10T428/24612 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method for forming alloy deposits at selected areas on a receiving substrate includes the steps of: providing an alloy carrier including at least a first decal including a first plurality of openings and a second decal including a second plurality of openings, the first and second decals being arranged such that each of the first plurality of openings is in alignment with a corresponding one of the second plurality of openings; filling the first and second plurality of openings with molten alloy; cooling the molten alloy to thereby form at least first and second plugs, the first plug having a first surface and a second surface substantially parallel to one another, the second plug having a third surface and a fourth surface substantially parallel to one another; removing at least one of the first and second decals to at least partially expose the first and second plugs; aligning the alloy carrier with the receiving substrate so that the first and second plugs correspond to the selected areas on the receiving substrate; and transferring the first plug to a first of the selected areas and the second plug to a second of the selected areas.

3. 发明申请

US20100072263A1 Method and Apparatus for Forming Planar Alloy Deposits on a Substrate 有权
标题翻译：在基体上形成平面合金沉积物的方法和装置
公开(公告)号：US20100072263A1
公开(公告)日：2010-03-25
申请号：US12627249
申请日：2009-11-30
申请人： Peter Alfred Gruber , Paul Alfred Lauro , Jae-Woong Nah
发明人： Peter Alfred Gruber , Paul Alfred Lauro , Jae-Woong Nah
IPC分类号： B23K1/20 , B23K31/02
CPC分类号： B23K1/0016 , H01L21/4853 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/0554 , H01L2224/05567 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/1183 , H01L2224/1184 , H01L2224/11848 , H01L2224/13099 , H01L2224/16225 , H01L2224/81192 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , Y10T428/24612 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method for forming alloy deposits at selected areas on a receiving substrate includes the steps of: providing an alloy carrier including at least a first decal including a first plurality of openings and a second decal including a second plurality of openings, the first and second decals being arranged such that each of the first plurality of openings is in alignment with a corresponding one of the second plurality of openings; filling the first and second plurality of openings with molten alloy; cooling the molten alloy to thereby form at least first and second plugs, the first plug having a first surface and a second surface substantially parallel to one another, the second plug having a third surface and a fourth surface substantially parallel to one another; removing at least one of the first and second decals to at least partially expose the first and second plugs; aligning the alloy carrier with the receiving substrate so that the first and second plugs correspond to the selected areas on the receiving substrate; and transferring the first plug to a first of the selected areas and the second plug to a second of the selected areas.
摘要翻译：一种用于在接收基板上的选定区域形成合金沉积物的方法，包括以下步骤：提供合金载体，该合金载体包括至少包括第一多个开口的第一贴花和包括第二多个开口的第二贴花，第一和第二贴花被布置成使得所述第一多个开口中的每一个与所述第二多个开口中的对应的一个开口对准; 用熔融合金填充第一和第二多个开口; 冷却所述熔融合金，从而形成至少第一和第二塞子，所述第一塞子具有基本上彼此平行的第一表面和第二表面，所述第二塞子具有基本上彼此平行的第三表面和第四表面; 去除所述第一和第二贴花中的至少一个以至少部分地暴露所述第一和第二插塞; 将合金载体与接收基板对准，使得第一和第二插塞对应于接收基板上的选定区域; 以及将所述第一插头转移到所选择的区域中的第一个，并且将所述第二插头转移到所选择的区域中的第二个。

4. 发明申请

US20100028612A1 Method and Apparatus for Forming Planar Alloy Deposits on a Substrate 有权
公开(公告)号：US20100028612A1
公开(公告)日：2010-02-04
申请号：US12181852
申请日：2008-07-29
申请人： Peter Alfred Gruber , Paul Alfred Lauro , Jae-Woong Nah
发明人： Peter Alfred Gruber , Paul Alfred Lauro , Jae-Woong Nah
IPC分类号： B32B3/02 , B23K31/02
CPC分类号： B23K1/0016 , H01L21/4853 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/0554 , H01L2224/05567 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/1183 , H01L2224/1184 , H01L2224/11848 , H01L2224/13099 , H01L2224/16225 , H01L2224/81192 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , Y10T428/24612 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method for forming alloy deposits at selected areas on a receiving substrate includes the steps of: providing an alloy carrier including at least a first decal including a first plurality of openings and a second decal including a second plurality of openings, the first and second decals being arranged such that each of the first plurality of openings is in alignment with a corresponding one of the second plurality of openings; filling the first and second plurality of openings with molten alloy; cooling the molten alloy to thereby form at least first and second plugs, the first plug having a first surface and a second surface substantially parallel to one another, the second plug having a third surface and a fourth surface substantially parallel to one another; removing at least one of the first and second decals to at least partially expose the first and second plugs; aligning the alloy carrier with the receiving substrate so that the first and second plugs correspond to the selected areas on the receiving substrate; and transferring the first plug to a first of the selected areas and the second plug to a second of the selected areas.

5. 发明授权

US08561880B2 Forming metal preforms and metal balls 有权
标题翻译：成型金属预制件和金属球
公开(公告)号：US08561880B2
公开(公告)日：2013-10-22
申请号：US13371430
申请日：2012-02-11
申请人： Peter Alfred Gruber , Paul Alfred Lauro , Jae-Woong Nah
发明人： Peter Alfred Gruber , Paul Alfred Lauro , Jae-Woong Nah
IPC分类号： B23K31/02
CPC分类号： B22D29/02 , B22C9/061 , B22D21/027 , B22D23/00 , B22D25/02
摘要： A process and tools for forming and/or releasing metal preforms, metal shapes and solder balls is described incorporating flexible molds or sheets, injection molded metal such as solder and in the case of solder balls, a liquid or gaseous environment to reduce or remove metal oxides prior to or during metal (solder) reflow to increase surface tension to form spherical or substantially spherical solder-balls.
摘要翻译：描述了用于形成和/或释放金属预成型件，金属形状和焊球的工艺和工具，其包括柔性模具或片材，注射成型金属如焊料，以及在焊球的情况下，液体或气体环境以减少或去除金属金属（焊料）回流之前或期间的氧化物，以增加表面张力以形成球形或基本上球形的焊球。

6. 发明授权

US08754666B2 Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof 失效
标题翻译：探头结构具有从支撑表面突出的多个离散的绝缘探针尖端，用于其的装置及其制造方法
公开(公告)号：US08754666B2
公开(公告)日：2014-06-17
申请号：US12052823
申请日：2008-03-21
申请人： Brian Samuel Beaman , Keith Edward Fogel , Paul Alfred Lauro , Yun-Hsin Liao , Daniel Peter Morris , Da-Yuan Shih
发明人： Brian Samuel Beaman , Keith Edward Fogel , Paul Alfred Lauro , Yun-Hsin Liao , Daniel Peter Morris , Da-Yuan Shih
IPC分类号： G01R1/067
CPC分类号： G01R1/07307 , G01R1/06711 , G01R1/0675 , G01R1/06772 , G01R1/07342 , G01R1/07371 , G01R1/07378 , G01R3/00 , G01R31/2886 , H01L23/49827 , H01L23/5384 , H01L25/0652 , H01L2224/1134 , H01L2224/13099 , H01L2224/16 , H01L2224/78301 , H01L2924/00013 , H01L2924/00014 , H01L2924/01014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/10253 , H01L2924/1627 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： Structures having a plurality of discrete insulated elongated electrical conductors projecting from a support surface which are useful as probes for testing of electrical interconnections to electronic devices, such as integrated circuit devices and other electronic components and particularly for testing of integrated circuit devices with rigid interconnection pads and multi-chip module packages with high density interconnection pads and the apparatus for use thereof and to methods of fabrication thereof. Coaxial probe structures are fabricated by the methods described providing a high density coaxial probe.
摘要翻译：具有从支撑表面突出的多个离散绝缘细长电导体的结构，其可用作用于测试电子装置（例如集成电路装置和其它电子部件）的电互连的探针，特别是用于测试具有刚性互连垫的集成电路装置以及具有高密度互连焊盘的多芯片模块封装及其使用的装置及其制造方法。通过提供高密度同轴探针的方法制造同轴探针结构。

7. 发明申请

US20100052715A1 HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF 审中-公开
公开(公告)号：US20100052715A1
公开(公告)日：2010-03-04
申请号：US12548537
申请日：2009-08-27
申请人： Brian Samuel Beaman , Keith Edward Fogel , Paul Alfred Lauro , Maurice Heathcote Norcott , Da-Yuan Shih , George Frederick Walker
发明人： Brian Samuel Beaman , Keith Edward Fogel , Paul Alfred Lauro , Maurice Heathcote Norcott , Da-Yuan Shih , George Frederick Walker
IPC分类号： G01R31/02 , G01R1/06
CPC分类号： G01R1/0735 , G01R1/06744 , G01R1/0675 , G01R1/07307 , G01R1/07378 , G01R3/00
摘要： The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.

8. 发明申请

US20100045320A1 HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF 审中-公开
公开(公告)号：US20100045320A1
公开(公告)日：2010-02-25
申请号：US12548567
申请日：2009-08-27
申请人： Brian Samuel Beaman , Keith Edward Fogel , Paul Alfred Lauro , Maurice Heathcote Norcott , Da-Yuan Shih , George Frederick Walker
发明人： Brian Samuel Beaman , Keith Edward Fogel , Paul Alfred Lauro , Maurice Heathcote Norcott , Da-Yuan Shih , George Frederick Walker
IPC分类号： G01R31/02 , G01R1/06
CPC分类号： G01R1/0735 , G01R1/06744 , G01R1/0675 , G01R1/07307 , G01R1/07378 , G01R3/00
摘要： The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.

9. 发明申请

US20090128176A1 HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF 审中-公开
标题翻译：高密度集成电路设备，测试探针及其使用方法
公开(公告)号：US20090128176A1
公开(公告)日：2009-05-21
申请号：US12357686
申请日：2009-01-22
申请人： Brian Samuel Beaman , Keith Edward Fogel , Paul Alfred Lauro , Maurice Heathcote Norcott , Da-Yuan Shin , George Frederick Walker
发明人： Brian Samuel Beaman , Keith Edward Fogel , Paul Alfred Lauro , Maurice Heathcote Norcott , Da-Yuan Shin , George Frederick Walker
IPC分类号： G01R1/067 , G01R31/02
CPC分类号： G01R1/07371 , G01R1/06711 , G01R1/0675 , G01R1/07307 , G01R1/07314 , G01R1/07342 , G01R1/07378 , G01R3/00 , G01R31/2886 , H01L23/49827 , H01L23/5384 , H01L24/45 , H01L24/48 , H01L25/0652 , H01L2224/1134 , H01L2224/13099 , H01L2224/16 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/45164 , H01L2224/48091 , H01L2224/48227 , H01L2224/78301 , H01L2224/85205 , H01L2224/85214 , H01L2924/00013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15192 , H01L2924/1627 , H01L2924/181 , H01L2924/19107 , H01L2924/3011 , Y10S29/029 , Y10T29/49004 , Y10T29/49126 , Y10T29/49147 , Y10T29/49149 , Y10T29/49158 , Y10T29/49162 , Y10T29/49192 , Y10T29/53174 , H01L2924/00 , H01L2924/00014 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076
摘要： The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.
摘要翻译：本发明涉及一种高密度测试探针，其提供用于测试晶片形式的高密度和高性能集成电路或作为离散芯片的装置。测试探针由嵌入柔性或高模量弹性体材料的细长电导体的密集阵列形成。使用陶瓷集成电路芯片封装基板等标准封装基板来提供空间变压器。电线被连接到空间变压器表面上的接触焊盘阵列。空间变压器由多层集成电路芯片封装基板形成。电线与接触位置阵列一样密集。围绕着向外突出的线的阵列设置模具。液体弹性体设置在模具中以填充电线之间的空间。弹性体被固化并且模具被去除，留下布置在弹性体中并且与空间变压器电接触的线阵列。空间变压器可以具有一组引脚，这些引脚位于空间变压器的相反表面上，其中细长导体被接合。这些销插入第二空间变压器（例如印刷电路板）上的插座中以形成探针组件。或者，插入器电连接器可以设置在第一和第二空间变压器之间。

10. 发明申请

US20080129319A1 HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF 审中-公开
标题翻译：高密度集成电路设备，测试探针及其使用方法
公开(公告)号：US20080129319A1
公开(公告)日：2008-06-05
申请号：US11930033
申请日：2007-10-30
申请人： Brian Samuel Beaman , Keith Edward Fogel , Paul Alfred Lauro , Maurice Heathcote Norcott , Da-Yuan Shih , George Frederick Walker
发明人： Brian Samuel Beaman , Keith Edward Fogel , Paul Alfred Lauro , Maurice Heathcote Norcott , Da-Yuan Shih , George Frederick Walker
IPC分类号： G01R31/02
CPC分类号： G01R1/0735 , G01R1/06744 , G01R1/0675 , G01R1/07307 , G01R1/07378 , G01R3/00
摘要： The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.
摘要翻译：本发明涉及一种高密度测试探针，其提供用于测试晶片形式的高密度和高性能集成电路或作为离散芯片的装置。测试探针由嵌入柔性或高模量弹性体材料的细长电导体的密集阵列形成。使用陶瓷集成电路芯片封装基板等标准封装基板来提供空间变压器。电线被连接到空间变压器表面上的接触焊盘阵列。空间变压器由多层集成电路芯片封装基板形成。电线与接触位置阵列一样密集。围绕着向外突出的线的阵列设置模具。液体弹性体设置在模具中以填充电线之间的空间。弹性体被固化并且模具被去除，留下布置在弹性体中并且与空间变压器电接触的线阵列。空间变压器可以具有一组引脚，这些引脚位于空间变压器的相反表面上，其中细长导体被接合。这些销插入第二空间变压器（例如印刷电路板）上的插座中以形成探针组件。或者，插入器电连接器可以设置在第一和第二空间变压器之间。

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