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1. 发明授权

US08139430B2 Power-on initialization and test for a cascade interconnect memory system 失效
标题翻译：级联互连存储器系统的上电初始化和测试
公开(公告)号：US08139430B2
公开(公告)日：2012-03-20
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G11C7/10 , G11C7/18
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译：用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。该接口可在SBC模式和高速模式下工作。存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。

2. 发明申请

US20100005281A1 POWER-ON INITIALIZATION AND TEST FOR A CASCADE INTERCONNECT MEMORY SYSTEM 失效
标题翻译：串联互连存储器系统的上电初始化和测试
公开(公告)号：US20100005281A1
公开(公告)日：2010-01-07
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G06F9/24
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译：用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。该接口可在SBC模式和高速模式下工作。存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。

3. 发明授权

US08234540B2 Error correcting code protected quasi-static bit communication on a high-speed bus 失效
标题翻译：在高速总线上纠错代码保护的准静态位通信
公开(公告)号：US08234540B2
公开(公告)日：2012-07-31
申请号：US12165788
申请日：2008-07-01
申请人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
发明人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
IPC分类号： H03M13/00
CPC分类号： H03M13/13 , G06F11/10
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译：提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。

4. 发明申请

US20100005365A1 ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS 失效
标题翻译：高速总线上的错误纠正代码保护的静态位通信
公开(公告)号：US20100005365A1
公开(公告)日：2010-01-07
申请号：US12165788
申请日：2008-07-01
申请人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
发明人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
IPC分类号： H03M13/09
CPC分类号： H03M13/13 , G06F11/10
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译：提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。

5. 发明申请

US20120272119A1 ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS 失效
标题翻译：高速总线上的错误纠正代码保护的静态位通信
公开(公告)号：US20120272119A1
公开(公告)日：2012-10-25
申请号：US13535574
申请日：2012-06-28
申请人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
发明人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
IPC分类号： H03M13/05 , G06F11/10 , H03M13/29
CPC分类号： H03M13/13 , G06F11/10
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译：提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。

6. 发明授权

US08516338B2 Error correcting code protected quasi-static bit communication on a high-speed bus 失效
标题翻译：在高速总线上纠错代码保护的准静态位通信
公开(公告)号：US08516338B2
公开(公告)日：2013-08-20
申请号：US13535574
申请日：2012-06-28
申请人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
发明人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
IPC分类号： H03M13/00
CPC分类号： H03M13/13 , G06F11/10
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译：提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。

7. 发明申请

US20090276559A1 Arrangements for Operating In-Line Memory Module Configurations 审中-公开
标题翻译：操作串行内存模块配置的安排
公开(公告)号：US20090276559A1
公开(公告)日：2009-11-05
申请号：US12114533
申请日：2008-05-02
申请人： James J. Allen, JR. , Robert J. Reese , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： James J. Allen, JR. , Robert J. Reese , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G06F12/06
CPC分类号： G06F13/1684 , G06F13/161
摘要： In one embodiment, a method is disclosed for timing responses to a plurality of memory requests. The method can include sending a plurality of memory requests to a plurality of in-line memory modules. The requests can be sent over a channel from a plurality of channels, where each channel can have a plurality of lanes. The method can receive responses to the plurality of memory requests over the channel and monitor the response to detect a timing relationship between at least two lanes from the plurality of lanes. In addition, the method can adjust a timing of a register loading and unloading sequence in response to the monitoring of multiple lanes and channels. Other embodiments are also disclosed.
摘要翻译：在一个实施例中，公开了一种用于对多个存储器请求进行定时响应的方法。该方法可以包括向多个在线存储器模块发送多个存储器请求。可以通过信道从多个信道发送请求，其中每个信道可以具有多个通道。该方法可以通过信道接收对多个存储器请求的响应，并监视响应以检测来自多个车道的至少两个车道之间的定时关系。此外，该方法可以响应于多个通道和通道的监视来调整寄存器加载和卸载序列的定时。还公开了其他实施例。

8. 发明授权

US08082475B2 Enhanced microprocessor interconnect with bit shadowing 有权
标题翻译：增强的微处理器互连与位阴影
公开(公告)号：US08082475B2
公开(公告)日：2011-12-20
申请号：US12165848
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F11/14 , G06F11/30
CPC分类号： G06F11/2007 , G06F11/0724 , G06F11/076 , H04L1/20
摘要： Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition shadow compare logic is used to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译：阴影选择逻辑用于选择驱动程序位位置作为阴影驱动程序值，线路驱动程序可以在总线的单独链路段上传输所选驱动程序位位置和阴影驱动程序值的数据。此外，阴影比较逻辑用于将选定的接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较，并且阴影计数器计数误差相对于总线错误率的速率经过一段时间。响应于在总线错误率的预定义阈值内的错误比较的速率来识别有缺陷的链路段。

9. 发明申请

US20100005202A1 DYNAMIC SEGMENT SPARING AND REPAIR IN A MEMORY SYSTEM 失效
标题翻译：动态部分在记忆系统中的分配和修复
公开(公告)号：US20100005202A1
公开(公告)日：2010-01-07
申请号：US12165809
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Ravi K. Arimilli , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Ravi K. Arimilli , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F3/00
CPC分类号： G06F13/4243 , G06F11/2007 , G06F11/2017 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译：用于在存储器系统中提供动态段保存和修复的通信接口设备，系统，方法和设计结构。通信接口装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段。

10. 发明申请

US20100005349A1 ENHANCED MICROPROCESSOR INTERCONNECT WITH BIT SHADOWING 有权
标题翻译：增强微处理器互连与位冲洗
公开(公告)号：US20100005349A1
公开(公告)日：2010-01-07
申请号：US12165848
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F11/00
CPC分类号： G06F11/2007 , G06F11/0724 , G06F11/076 , H04L1/20
摘要： A processing device, processing system, method, and design structure for an enhanced microprocessor interconnect with bit shadowing are provided. The processing device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The processing device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译：提供了一种用于具有位阴影的增强型微处理器互连的处理装置，处理系统，方法和设计结构。处理装置包括阴影选择逻辑以选择驱动器位位置作为阴影驱动器值，以及线驱动器，用于在总线的单独链路段上传送所选择的驱动器位位置和阴影驱动器值的数据。处理装置还包括阴影比较逻辑，以将所选接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较，并且阴影计数器计数误差相对于总线误差的速率率一段时间。响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。

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