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1. 发明授权

US08139430B2 Power-on initialization and test for a cascade interconnect memory system 失效
标题翻译：级联互连存储器系统的上电初始化和测试
公开(公告)号：US08139430B2
公开(公告)日：2012-03-20
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G11C7/10 , G11C7/18
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译：用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。该接口可在SBC模式和高速模式下工作。存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。

2. 发明申请

US20100005281A1 POWER-ON INITIALIZATION AND TEST FOR A CASCADE INTERCONNECT MEMORY SYSTEM 失效
标题翻译：串联互连存储器系统的上电初始化和测试
公开(公告)号：US20100005281A1
公开(公告)日：2010-01-07
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G06F9/24
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译：用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。该接口可在SBC模式和高速模式下工作。存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。

3. 发明授权

US07793143B2 Switching a defective signal line with a spare signal line without shutting down the computer system 失效
标题翻译：在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线
公开(公告)号：US07793143B2
公开(公告)日：2010-09-07
申请号：US12098294
申请日：2008-04-04
申请人： Edgar R. Cordero , James S. Fields, Jr. , Kevin C. Gower , Eric E. Retter
发明人： Edgar R. Cordero , James S. Fields, Jr. , Kevin C. Gower , Eric E. Retter
IPC分类号： G06F11/00
CPC分类号： G06F11/10 , G06F11/2007 , G11C29/025 , G11C2029/0409
摘要： A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.
摘要翻译：一种用于在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线的方法，计算机程序产品和系统。服务处理器监视配置成检测信号线中的错误的纠错码（ECC）检查单元。如果ECC检查单元检测到错误率超过阈值，则具有这种错误率的信号线可能被认为是“有缺陷的”。服务处理器配置与缺陷信号相关联的驱动器/接收器对中的开关控制单元线路，以便在从存储器控制器开关控制单元接收到命令时能够用备用线路切换有缺陷的信号线。以这种方式，为了用备用线切换有缺陷的信号线，系统不被去激活，从而减少处理器不能向存储器缓冲器发送信息的时间。

4. 发明授权

US07380161B2 Switching a defective signal line with a spare signal line without shutting down the computer system 失效
标题翻译：在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线
公开(公告)号：US07380161B2
公开(公告)日：2008-05-27
申请号：US11056886
申请日：2005-02-11
申请人： Edgar R. Cordero , James S. Fields, Jr. , Kevin C. Gower , Eric E. Retter
发明人： Edgar R. Cordero , James S. Fields, Jr. , Kevin C. Gower , Eric E. Retter
IPC分类号： G06F11/00
CPC分类号： G06F11/10 , G06F11/2007 , G11C29/025 , G11C2029/0409
摘要： A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.
摘要翻译：一种用于在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线的方法，计算机程序产品和系统。服务处理器监视配置成检测信号线中的错误的纠错码（ECC）检查单元。如果ECC检查单元检测到错误率超过阈值，则具有这种错误率的信号线可能被认为是“有缺陷的”。服务处理器配置与缺陷信号线相关联的驱动器/接收器对中的开关控制单元，以便在从存储器控制器开关控制单元接收到命令时能够用备用线切换故障信号线。以这种方式，为了用备用线切换有缺陷的信号线，系统不被去激活，从而减少处理器不能向存储器缓冲器发送信息的时间。

5. 发明申请

US20080215929A1 SWITCHING A DEFECTIVE SIGNAL LINE WITH A SPARE SIGNAL LINE WITHOUT SHUTTING DOWN THE COMPUTER SYSTEM 失效
标题翻译：切换带有备用信号线的有缺陷的信号线，而不需要切断计算机系统
公开(公告)号：US20080215929A1
公开(公告)日：2008-09-04
申请号：US12098294
申请日：2008-04-04
申请人： Edgar R. Cordero , James S. Fields , Kevin C. Gower , Eric E. Retter
发明人： Edgar R. Cordero , James S. Fields , Kevin C. Gower , Eric E. Retter
IPC分类号： G06F11/00
CPC分类号： G06F11/10 , G06F11/2007 , G11C29/025 , G11C2029/0409
摘要： A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.
摘要翻译：一种用于在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线的方法，计算机程序产品和系统。服务处理器监视配置成检测信号线中的错误的纠错码（ECC）检查单元。如果ECC检查单元检测到错误率超过阈值，则具有这种错误率的信号线可能被认为是“有缺陷的”。服务处理器配置与缺陷信号线相关联的驱动器/接收器对中的开关控制单元，以便在从存储器控制器开关控制单元接收到命令时能够用备用线切换故障信号线。以这种方式，为了用备用线切换有缺陷的信号线，系统不被去激活，从而减少处理器不能向存储器缓冲器发送信息的时间。

6. 发明申请

US20090216985A1 METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR DYNAMIC SELECTIVE MEMORY MIRRORING 有权
标题翻译：用于动态选择记忆镜的方法，系统和计算机程序产品
公开(公告)号：US20090216985A1
公开(公告)日：2009-08-27
申请号：US12035695
申请日：2008-02-22
申请人： James A. O'Connor , Kanwal Bahri , Daniel J. Henderson , Luis A. Lastras-Montano , Warren E. Maule , Michael Mueller , Naresh Nayar , Richard Nicholas , Eric E. Retter , William J. Starke , Michael R. Trombley , Kenneth L. Wright
发明人： James A. O'Connor , Kanwal Bahri , Daniel J. Henderson , Luis A. Lastras-Montano , Warren E. Maule , Michael Mueller , Naresh Nayar , Richard Nicholas , Eric E. Retter , William J. Starke , Michael R. Trombley , Kenneth L. Wright
IPC分类号： G06F12/02
CPC分类号： G06F11/1666 , G06F11/1076 , G06F11/20 , G06F12/0246 , G06F2211/1088
摘要： Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections of the memory are mirrored in the reserved memory.
摘要翻译：为固态设备中的动态选择性存储器镜像提供了方法，系统和计算机程序产品。保留一定量的内存。用于在保留的存储器中选择镜像的存储器的部分是动态确定的。存储器的选定部分包含关键区域。存储器的选定部分被镜像在保留的存储器中。

7. 发明申请

US20100299576A1 System to Improve Miscorrection Rates in Error Control Code Through Buffering and Associated Methods 失效
标题翻译：系统通过缓冲和相关方法提高错误控制代码的误码率
公开(公告)号：US20100299576A1
公开(公告)日：2010-11-25
申请号：US12023516
申请日：2008-01-31
申请人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1044
摘要： A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.
摘要翻译：用于改善错误控制代码中的错误率的系统可以包括处理至少两个数据分组的具有安全解码模式的错误控制解码器。系统还可以包括缓冲器，以从误差控制解码器接收经处理的至少两个数据分组。误差控制解码器可以对与至少两个数据分组的处理相关的不可校正误差信号应用逻辑或运算，以产生全局不可校正的误差信号。系统还可以包括接收器以接收至少两个数据分组和全局不可校正的误差信号。

8. 发明申请

US20100293438A1 System to Improve Error Correction Using Variable Latency and Associated Methods 有权
标题翻译：使用变量延迟和相关方法改进误差校正的系统
公开(公告)号：US20100293438A1
公开(公告)日：2010-11-18
申请号：US12023546
申请日：2008-01-31
申请人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1048
摘要： A system to improve error correction may include a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system may also include a slow decoder to possibly correct the uncorrectable error in a data packet based upon the at least two data packets.
摘要翻译：用于改进纠错的系统可以包括处理数据分组的快速解码器，直到快速解码器在数据分组中发现对于至少两个数据分组的请求产生的不可校正的错误。该系统还可以包括慢解码器，以可能地基于至少两个数据分组校正数据分组中的不可校正错误。

9. 发明申请

US20100287436A1 System for Error Decoding with Retries and Associated Methods 有权
标题翻译：使用重试和关联方法进行错误解码的系统
公开(公告)号：US20100287436A1
公开(公告)日：2010-11-11
申请号：US12023356
申请日：2008-01-31
申请人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winogard
发明人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winogard
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1044 , G06F11/08 , G06F11/14 , H04W4/00 , H04W28/04
摘要： A system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue.
摘要翻译：通过重试来改进错误代码解码的系统可以包括请求数据分组的处理单元和用于保存用于处理单元的数据分组的队列。系统还可以包括解码器，用于基于每个数据分组中的任何错误来确定队列中每个数据分组的处理时间，并且如果特定数据分组的处理时间大于阈值，则更新对于队列中的数据包。

10. 发明授权

US08181094B2 System to improve error correction using variable latency and associated methods 有权
标题翻译：使用可变延迟和相关方法改进纠错的系统
公开(公告)号：US08181094B2
公开(公告)日：2012-05-15
申请号：US12023546
申请日：2008-01-31
申请人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/00
CPC分类号： G06F11/1048
摘要： A system to improve error correction includes a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system also includes a slow decoder to correct the uncorrectable error in a data packet based upon the at least two data packets.
摘要翻译：改进纠错的系统包括处理数据分组的快速解码器，直到快速解码器在数据分组中发现不可校正的错误，在该时间点产生对至少两个数据分组的请求。该系统还包括缓慢解码器，用于基于至少两个数据分组校正数据分组中的不可校正错误。

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