专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07915155B2 Double trench for isolation of semiconductor devices 有权
标题翻译：用于隔离半导体器件的双沟槽
公开(公告)号：US07915155B2
公开(公告)日：2011-03-29
申请号：US12651683
申请日：2010-01-04
申请人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
发明人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
IPC分类号： H01L21/22
CPC分类号： H01L21/3081 , H01L21/3083 , H01L21/76205 , H01L21/76229
摘要： Semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other pails of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.
摘要翻译：半导体器件具有衬底（50），掩埋层（55），从表面接触延伸到掩埋层的有源区，在朝向掩埋层延伸的第一沟槽中的绝缘体（130），以隔离有源区，以及在第二深沟槽中的第二绝缘体（130），并且延伸穿过所述掩埋层以将所述掩埋层和所述有源区域与所述衬底的其它桶隔离。该双沟槽可以帮助减少有源器件与其他器件之间的电气隔离所需的面积。这样的面积减少可以实现多单元超MOS器件中的更大的集成或更多的单元，并且因此改进诸如Ron的性能参数。可以使用第一掩模制造双沟槽以同时蚀刻两个沟槽，并且随后使用第二掩模来更深地蚀刻第二深沟槽。

2. 发明申请

US20100105188A1 DOUBLE TRENCH FOR ISOLATION OF SEMICONDUCTOR DEVICES 有权
标题翻译：用于隔离半导体器件的双光栅
公开(公告)号：US20100105188A1
公开(公告)日：2010-04-29
申请号：US12651683
申请日：2010-01-04
申请人： Peter MOENS , Marnix Tack , Sylvie Boonen , Paul Colson
发明人： Peter MOENS , Marnix Tack , Sylvie Boonen , Paul Colson
IPC分类号： H01L21/762
CPC分类号： H01L21/3081 , H01L21/3083 , H01L21/76205 , H01L21/76229
摘要： Semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other pails of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.
摘要翻译：半导体器件具有衬底（50），掩埋层（55），从表面接触延伸到掩埋层的有源区，在朝向掩埋层延伸的第一沟槽中的绝缘体（130），以隔离有源区，以及在第二深沟槽中的第二绝缘体（130），并且延伸穿过所述掩埋层以将所述掩埋层和所述有源区域与所述衬底的其它桶隔离。该双沟槽可以帮助减少有源器件与其他器件之间的电气隔离所需的面积。这样的面积减少可以实现多单元超MOS器件中的更大的集成或更多的单元，并且因此改进诸如Ron的性能参数。可以使用第一掩模制造双沟槽以同时蚀刻两个沟槽，并且随后使用第二掩模来更深地蚀刻第二深沟槽。

3. 发明授权

US07667270B2 Double trench for isolation of semiconductor devices 有权
标题翻译：用于隔离半导体器件的双沟槽
公开(公告)号：US07667270B2
公开(公告)日：2010-02-23
申请号：US11399377
申请日：2006-04-07
申请人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
发明人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
IPC分类号： H01L21/331
CPC分类号： H01L21/3081 , H01L21/3083 , H01L21/76205 , H01L21/76229
摘要： A semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other parts of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.
摘要翻译：半导体器件具有衬底（50），掩埋层（55），从表面接触延伸到掩埋层的有源区，在朝向掩埋层延伸的第一沟槽中的绝缘体（130），以隔离有源区，以及第二深沟槽中的第二绝缘体（130），并延伸穿过所述掩埋层以将所述掩埋层和所述有源区域与所述衬底的其它部分隔离。该双沟槽可以帮助减少有源器件与其他器件之间的电气隔离所需的面积。这样的面积减少可以实现多单元超MOS器件中的更大的集成或更多的单元，并且因此改进诸如Ron的性能参数。可以使用第一掩模制造双沟槽以同时蚀刻两个沟槽，并且随后使用第二掩模来更深地蚀刻第二深沟槽。

4. 发明申请

US20060244029A1 Double trench for isolation of semiconductor devices 有权
标题翻译：用于隔离半导体器件的双沟槽
公开(公告)号：US20060244029A1
公开(公告)日：2006-11-02
申请号：US11399377
申请日：2006-04-07
申请人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
发明人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119 , H01L21/76
CPC分类号： H01L21/3081 , H01L21/3083 , H01L21/76205 , H01L21/76229
摘要： A semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other parts of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.
摘要翻译：半导体器件具有衬底（50），掩埋层（55），从表面接触延伸到掩埋层的有源区，在朝向掩埋层延伸的第一沟槽中的绝缘体（130），以隔离有源区，以及第二深沟槽中的第二绝缘体（130），并延伸穿过所述掩埋层以将所述掩埋层和所述有源区域与所述衬底的其它部分隔离。该双沟槽可以帮助减少有源器件与其他器件之间的电气隔离所需的面积。这样的面积减少可以实现多单元超MOS器件中的更大的集成或更多的单元，并且因此改进诸如Ron的性能参数。可以使用第一掩模制造双沟槽以同时蚀刻两个沟槽，并且随后使用第二掩模来更深地蚀刻第二深沟槽。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式