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    • 7. 发明授权
    • High-performance multiple port memory
    • 高性能多端口存储器
    • US4766535A
    • 1988-08-23
    • US811624
    • 1985-12-20
    • Daniel J. AuerbachTien C. ChenWolfgang J. Paul
    • Daniel J. AuerbachTien C. ChenWolfgang J. Paul
    • G06F12/06G06F9/30G06F12/04G06F15/78G06F12/00G06F13/00G06F13/38
    • G06F9/30138G06F15/8053
    • Disclosed is a multiple port memory apparatus responsive to r+w addresses within an instruction cycle for supplying data read from the r read addresses and for writing data received to the w write addresses. The memory apparatus comprises r groups of w+1 memory banks, responsive to the r read addresses and the w write addresses, for supplying for each of the r read addresses data read from one of the w+1 banks in one of the r groups and for writing data received to each of the w write addresses in the other of the w+1 banks in the r groups. A pointer for controlling the r groups of w+1 memory banks directs the read and write accesses to the memory banks so that one of the w+1 banks obtaining valid data is read in response to a read address and so that data is written to the other banks in each cycle.The pointer directs memory accessing to prevent conflicts. Conflicts are always avoided because one bank in each of the r groups is directed to supply data in response to a read address and the w remaining banks are available for writing data in response to the w write addresses redundantly so that each of the groups of memory banks will have valid data in at least one of its w+1 memory banks for a given address.
    • 公开了一种响应于指令周期内的r + w地址的多端口存储器装置,用于提供从r个读取地址读取的数据并将接收到的数据写入w个写入地址。 存储器装置包括r组的w + 1个存储体,响应于r个读取地址和w个写入地址,为r个读取地址中的每一个提供从r组中的一个中的w + 1个存储体之一读取的数据 并且用于将接收到的数据写入r组中的另一个w + 1个存储体中的每个w写地址。 用于控制w + 1个存储器组的r组的指针指示对存储体的读取和写入访问,以便响应于读取地址读取获得有效数据的w + 1组之一,并且将数据写入 其他银行在每个周期。 指针指示内存访问以防止冲突。 总是避免冲突,因为r组中的每个组中的一个组针对读取地址而提供数据,并且w个剩余存储体可用于冗余地响应于w写入地址而写入数据,使得存储器组中的每一组 银行将在给定地址的至少其中一个w + 1存储器中存储有效数据。