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1. 发明申请

US20120182795A1 EMULATION OF STATIC RANDOM ACCESS MEMORY (SRAM) BY MAGNETIC RANDOM ACCESS MEMORY (MRAM) 有权
标题翻译：通过磁性随机存取存储器（MRAM）对静态随机存取存储器（SRAM）进行仿真
公开(公告)号：US20120182795A1
公开(公告)日：2012-07-19
申请号：US13187402
申请日：2011-07-20
申请人： Petro Estakhri , Ebrahim Abedifard , Frederick Jaffin , Siamack Nemazie
发明人： Petro Estakhri , Ebrahim Abedifard , Frederick Jaffin , Siamack Nemazie
IPC分类号： G11C11/02
CPC分类号： G11C11/1673 , G11C7/1042 , G11C8/04 , G11C11/1653 , G11C11/1675 , G11C11/1693
摘要： A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks.
摘要翻译：磁存储器系统包括包括多个磁存储器组的磁随机存取存储器（MRAM），并且可操作以在由写命令发起的写操作期间存储数据。磁存储器系统还包括耦合到MRAM并且包括多个FIFO的先进先出（FIFO）接口设备。每个磁存储器组耦合到多个FIFO中的相应一个，FIFO是可操作地在每个磁存储体的基础上排队写入命令，并进一步操作以在不使用MRAM时发出排队的写入命令，其中并行写入操作被执行到多个磁存储器组中的至少两个。

2. 发明授权

US08755221B2 Emulation of static random access memory (SRAM) by magnetic random access memory (MRAM) 有权
标题翻译：磁性随机存取存储器（MRAM）对静态随机存取存储器（SRAM）的仿真
公开(公告)号：US08755221B2
公开(公告)日：2014-06-17
申请号：US13187402
申请日：2011-07-20
申请人： Petro Estakhri , Ebrahim Abedifard , Frederick Jaffin , Siamack Nemazie
发明人： Petro Estakhri , Ebrahim Abedifard , Frederick Jaffin , Siamack Nemazie
IPC分类号： G11C11/14
CPC分类号： G11C11/1673 , G11C7/1042 , G11C8/04 , G11C11/1653 , G11C11/1675 , G11C11/1693
摘要： A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks.
摘要翻译：磁存储器系统包括包括多个磁存储器组的磁随机存取存储器（MRAM），并且可操作以在由写命令发起的写操作期间存储数据。磁存储器系统还包括耦合到MRAM并且包括多个FIFO的先进先出（FIFO）接口设备。每个磁存储器组耦合到多个FIFO中的相应一个，FIFO是可操作地在每个磁存储体的基础上排队写入命令，并进一步操作以在不使用MRAM时发出排队的写入命令，其中并行写入操作被执行到多个磁存储器组中的至少两个。

3. 发明申请

US20130007544A1 MAPPING OF RANDOM DEFECTS IN A MEMORY DEVICE 有权
公开(公告)号：US20130007544A1
公开(公告)日：2013-01-03
申请号：US13175801
申请日：2011-07-01
申请人： Siamack Nemazie , Ebrahim Abedifard
发明人： Siamack Nemazie , Ebrahim Abedifard
IPC分类号： G06F11/07 , G06F11/20
CPC分类号： G11C29/72 , G06F3/0619 , G06F3/0638 , G06F3/0679 , G06F11/2094 , G06F2212/1032 , G11C29/4401 , G11C29/808
摘要： A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.

4. 发明授权

US08385108B1 Differential magnetic random access memory (MRAM) 有权
标题翻译：差分磁随机存取存储器（MRAM）
公开(公告)号：US08385108B1
公开(公告)日：2013-02-26
申请号：US13429293
申请日：2012-03-23
申请人： Ebrahim Abedifard , Siamack Nemazie , Parviz Keshtbod
发明人： Ebrahim Abedifard , Siamack Nemazie , Parviz Keshtbod
IPC分类号： G11C11/00
CPC分类号： G11C11/14 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1697
摘要： A method of method of writing to a magnetic memory cell includes selecting a magnetic memory cell of a magnetic memory array to be written to, the magnetic memory cell including a pair of MTJs, and setting a bit line (BL) coupled to the magnetic memory cell to a state that causes current to flow through the pair of MTJs in a manner that causes the direction of current flow through one of the MTJs of the pair of MTJs to be in a direction opposite to that of the other MTJ of the pair of MTJs.
摘要翻译：写入磁存储单元的方法的方法包括选择要写入的磁存储器阵列的磁存储单元，磁存储单元包括一对MTJ，以及设置耦合到磁存储器的位线（BL）电池导致电流流过该对MTJ的状态，使得电流流过该对MTJ的MTJ之一的电流的方向处于与该对MTJ的另一个MTJ的方向相反的方向 MTJs。

5. 发明授权

US08887013B2 Mapping of random defects in a memory device 有权
标题翻译：映射存储器件中的随机缺陷
公开(公告)号：US08887013B2
公开(公告)日：2014-11-11
申请号：US13175801
申请日：2011-07-01
申请人： Siamack Nemazie , Ebrahim Abedifard
发明人： Siamack Nemazie , Ebrahim Abedifard
IPC分类号： G11C29/00
CPC分类号： G11C29/72 , G06F3/0619 , G06F3/0638 , G06F3/0679 , G06F11/2094 , G06F2212/1032 , G11C29/4401 , G11C29/808
摘要： A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.
摘要翻译：存储器件包括具有随机缺陷存储器单元的存储器阵列。存储器阵列被组织成具有标识存储器阵列的存储器单元的存储器位置的行和列的行和列。存储器件包括行地址设备和列地址设备，并且可操作地使用行或列地址的分组来通过将缺陷存储器单元的存储器位置映射到备用存储器位置来管理随机缺陷存储器单元。

6. 发明授权

US09520174B2 Method and apparatus for writing to a magnetic tunnel junction (MTJ) by applying incrementally increasing voltage level 有权
公开(公告)号：US09520174B2
公开(公告)日：2016-12-13
申请号：US14754635
申请日：2015-06-29
申请人： Ebrahim Abedifard , Petro Estakhri
发明人： Ebrahim Abedifard , Petro Estakhri
IPC分类号： G11C11/00 , G11C11/16 , G11C11/56
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1677 , G11C11/1693 , G11C11/5607
摘要： A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ.

7. 发明授权

US09070458B2 Method and apparatus for writing to a magnetic tunnel junction (MTJ) by applying incrementally increasing voltage level 有权
标题翻译：通过施加逐渐增加的电压电平来写入磁性隧道结（MTJ）的方法和装置
公开(公告)号：US09070458B2
公开(公告)日：2015-06-30
申请号：US13481097
申请日：2012-05-25
申请人： Ebrahim Abedifard , Petro Estakhri
发明人： Ebrahim Abedifard , Petro Estakhri
IPC分类号： G11C11/00 , G11C11/16 , G11C11/56
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1677 , G11C11/1693 , G11C11/5607
摘要： A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ.
摘要翻译：写入磁存储器阵列的磁隧道结（MTJ）的方法包括将缓存数据存储在高速缓存寄存器中，读取至少两个MTJ的集合中的第一个的当前逻辑状态，该集合至少两个MTJ，包括第一个MTJ和第二个MTJ。即将发送的数据将被写入第二个MTJ。进一步的步骤是将读逻辑状态存储到数据寄存器中，交换数据寄存器和高速缓存寄存器的内容，使得高速缓存寄存器存储读逻辑状态，数据寄存器存储进来数据，施加第一预定电压电平到MTJ集合，从而使第一MTJ被重写，向MTJ集合施加第二预定电压电平，并将进入的数据存储到第二MTJ中。

8. 发明授权

US08687418B1 Flash memory with nano-pillar charge trap 有权
标题翻译：闪存与纳米柱电荷陷阱
公开(公告)号：US08687418B1
公开(公告)日：2014-04-01
申请号：US12623369
申请日：2009-11-20
申请人： Rajiv Yadav Ranjan , Ebrahim Abedifard , Petro Estakhri , Parviz Keshtbod
发明人： Rajiv Yadav Ranjan , Ebrahim Abedifard , Petro Estakhri , Parviz Keshtbod
IPC分类号： G11C11/34
CPC分类号： H01F41/303 , B82Y10/00 , B82Y25/00 , B82Y40/00 , G11C11/161 , H01F10/3236 , H01F10/3254 , H01F10/3272 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/42332 , H01L29/7881
摘要： An embodiment of the present invention includes a non-volatile storage unit comprising a first and second N-diffusion well separated by a distance of P-substrate. A first isolation layer is formed upon the first and second N-diffusion wells and the P-substrate. A nano-pillar charge trap layer is formed upon the first isolation layer and includes conductive nano-pillars interspersed between non-conducting regions. The storage unit further includes a second isolation layer formed upon the nano-pillar charge trap layer; and at least one word line formed upon the second isolation layer and above a region of nano-pillar charge trap layer. The nano-pillar charge trap layer is operative to trap charge upon application of a threshold voltage. Subsequently, the charge trap layer may be read to determine any charge stored in the non-volatile storage unit, where presence or absence of stored charge in the charge trap layer corresponds to a bit value.
摘要翻译：本发明的实施例包括非易失性存储单元，其包括以P基底间隔开的第一和第二N-扩散阱。在第一和第二N-扩散阱和P-基底上形成第一隔离层。纳米柱电荷陷阱层形成在第一隔离层上，并且包括散布在非导电区域之间的导电纳米柱。存储单元还包括形成在纳米柱电荷陷阱层上的第二隔离层; 以及形成在第二隔离层上方和纳米柱电荷陷阱层的区域上方的至少一个字线。纳米柱电荷陷阱层可用于在施加阈值电压时捕获电荷。随后，可以读取电荷陷阱层以确定存储在非易失性存储单元中的任何电荷，其中电荷陷阱层中存在或不存在电荷对应于位值。

9. 发明授权

US08363460B2 Method and apparatus for programming a magnetic tunnel junction (MTJ) 有权
标题翻译：用于编程磁隧道结（MTJ）的方法和装置
公开(公告)号：US08363460B2
公开(公告)日：2013-01-29
申请号：US12826546
申请日：2010-06-29
申请人： Ebrahim Abedifard , Petro Estakhri
发明人： Ebrahim Abedifard , Petro Estakhri
IPC分类号： G11C11/00 , G11C11/14 , G11C11/15
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1677 , G11C11/1693 , G11C11/5607
摘要： A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ.
摘要翻译：写入磁存储器阵列的磁隧道结（MTJ）的方法包括将缓存数据存储在高速缓存寄存器中，读取至少两个MTJ的集合中的第一个的当前逻辑状态，该集合至少两个MTJ，包括第一个MTJ和第二个MTJ。即将发送的数据将被写入第二个MTJ。进一步的步骤是将读逻辑状态存储到数据寄存器中，交换数据寄存器和高速缓存寄存器的内容，使得高速缓存寄存器存储读逻辑状态，数据寄存器存储进来数据，施加第一预定电压电平到MTJ集合，从而使第一MTJ被重写，向MTJ集合施加第二预定电压电平，并将进入的数据存储到第二MTJ中。

10. 发明申请

US20070263449A1 Method and apparatus for programming flash memory 有权
标题翻译：用于编程闪存的方法和装置
公开(公告)号：US20070263449A1
公开(公告)日：2007-11-15
申请号：US11433562
申请日：2006-05-15
申请人： Erwin Yu , Ebrahim Abedifard , Frederick Jaffin , Uday Chandrasekhar
发明人： Erwin Yu , Ebrahim Abedifard , Frederick Jaffin , Uday Chandrasekhar
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/12 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array using a minimum number of programming pulses.
摘要翻译：一种提供在闪速存储器件中控制具有不同宽度和/或电压的编程脉冲的能力的方法和装置。设置编程脉冲的宽度和/或电压电平以使用最少数量的编程脉冲对阵列的所有存储单元进行编程。

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