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1. 发明授权

US08443322B2 Using layout enumeration to facilitate integrated circuit development 失效
标题翻译：使用布局枚举来促进集成电路开发
公开(公告)号：US08443322B2
公开(公告)日：2013-05-14
申请号：US12406996
申请日：2009-03-19
申请人： Philip N. Strenski , Mark A. Lavin
发明人： Philip N. Strenski , Mark A. Lavin
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22
CPC分类号： G06F17/5068
摘要： A method for using layout enumeration to facilitate integrated circuit development includes defining an initial set of design ground rules represented in a notation compatible with a coarse placement grid, for a given layer(s) of an integrated circuit device; defining an initial region of interest for the integrated circuit device; enumerating, according to the initial set of design ground rules, each legal design layout for a given layer of the integrated circuit device in the initial region of interest; running a manufacturing simulation of the enumerated legal design layout data and, responsive to determining one or more failing layouts resulting therefrom, further determining whether the failing layouts may be eliminated by changes in technology parameters and/or updated ground rules. Upon eliminating the one or more failing layouts for the initial region of interest, expanding the initial region of interest and repeating the enumerating, manufacturing simulation, and triage assessment.
摘要翻译：一种用于使用布局枚举以促进集成电路开发的方法包括：为集成电路器件的给定层定义以与粗放置网格兼容的符号表示的设计基准规则的初始集合; 定义集成电路器件的初始感兴趣区域; 列举根据初始设计基准规则，每个法定设计布局为集成电路设备在给定层的初始区域感兴趣; 运行枚举的法律设计布局数据的制造模拟，并且响应于确定由此产生的一个或多个故障布局，进一步确定是否可以通过技术参数和/或更新的基本规则的改变来消除故障布局。在消除初始感兴趣区域的一个或多个失败的布局后，扩展初始的兴趣区域，并重复枚举，制造模拟和分类评估。

2. 发明申请

US20120311515A1 Method For Performing A Parallel Static Timing Analysis Using Thread-Specific Sub-Graphs 有权
标题翻译：使用线程特定子图执行并行静态时序分析的方法
公开(公告)号：US20120311515A1
公开(公告)日：2012-12-06
申请号：US13151295
申请日：2011-06-02
申请人： Vladimir Zolotov , David J. Hathaway , Kerim Kalafala , Mark A. Lavin , Peihua Qi
发明人： Vladimir Zolotov , David J. Hathaway , Kerim Kalafala , Mark A. Lavin , Peihua Qi
IPC分类号： G06F9/455
CPC分类号： G06F17/5031 , G06F8/20 , G06F2217/84
摘要： A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task. As all data structures of each child thread are accessed only by the child thread owing them, no access locks are required for construction and processing of thread specific graph replica of the timing sub-graph. The construction of each thread specific graph replica is performed by the child thread without locking the main timing graph data structures. Access locks are used only for transferring results of the analysis back to the main timing graph where the results computed by all child threads are combined together.
摘要翻译：描述了一种用于定时图的有效多线程分析的方法。该方法适用于多线程公共路径悲观消除，定时报告生成的关键路径遍历以及需要遍历时序图子图的其他类型分析。为了实现并行多线程执行的高效率和可扩展性，访问锁的数量最小化。使用一个父计算线程和多个子线程。父计算线程识别用于分析的任务，并在子线程之间分配它们。每个子线程标识要分析的子图，创建所识别的子图的线程特定副本，并执行所需的分析。完成分析后，子线程将结果传回主时序图，等待下一个任务。由于每个子线程的所有数据结构仅由它们的子线程访问，所以不需要访问锁来构建和处理定时子图的线程特定图形副本。每个线程特定图形副本的构造由子线程执行，而不锁定主时序图数据结构。访问锁仅用于将分析结果传回主时序图，其中所有子线程计算的结果组合在一起。

3. 发明申请

US20120167029A1 PHYSICAL DESIGN SYSTEM AND METHOD 失效
标题翻译：物理设计系统与方法
公开(公告)号：US20120167029A1
公开(公告)日：2012-06-28
申请号：US13413759
申请日：2012-03-07
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
摘要翻译：一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。布局单元接收表示网格和字形格式的部分的电路描述。检查单元检查设计的网格和字形部分。精心设计单元从检查的设计生成目标布局。数据准备单元准备掩模制作的目标布局。模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

4. 发明授权

US07823094B2 Pseudo-string based pattern recognition in L3GO designs 有权
标题翻译： L3GO设计中基于伪串的模式识别
公开(公告)号：US07823094B2
公开(公告)日：2010-10-26
申请号：US11621383
申请日：2007-01-09
申请人： Ulrich A. Finkler , Mark A. Lavin , Robert T. Sayah
发明人： Ulrich A. Finkler , Mark A. Lavin , Robert T. Sayah
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/504 , G06F2217/12 , Y02P90/265
摘要： A system and method for processing glyph-based data associated with generating very large scale integrated circuit (VLSI) designs. A system is provide that includes a serialization system for converting an input region of glyph design data into a pseudo-string; and a pattern searching system that identifies matching patterns in the glyph design data by analyzing pseudo-strings generated by the serialization system. Pattern searching may include, e.g., predefined pattern searching and redundant pattern searching.
摘要翻译：一种用于处理与生成超大规模集成电路（VLSI）设计相关联的基于字形的数据的系统和方法。提供一种系统，其包括用于将字形设计数据的输入区域转换为伪字符串的串行化系统; 以及通过分析由串行化系统生成的伪串来识别字形设计数据中的匹配模式的模式搜索系统。模式搜索可以包括例如预定义模式搜索和冗余模式搜索。

5. 发明申请

US20090180711A1 RENDERING A MASK USING COARSE MASK REPRESENTATION 有权
标题翻译：使用粗糙表示渲染一个掩码
公开(公告)号：US20090180711A1
公开(公告)日：2009-07-16
申请号：US12015084
申请日：2008-01-16
申请人： Mark A. Lavin , Maharaj Mukherjee , Alan E. Rosenbluth
发明人： Mark A. Lavin , Maharaj Mukherjee , Alan E. Rosenbluth
IPC分类号： G06K9/36
CPC分类号： G03F7/705 , G03F1/36
摘要： A method, system and computer program product for rendering a mask are disclosed. A method of rendering a mask may comprise: providing an initial mask design for a photolithographic process, the initial mask design including polygons; initially rendering the initial mask design as a coarse mask representation in a pixel based image calculation; identifying an overhang portion; and rendering the overhang portion using a set of subpixels whose artifacts from spatial-localization lie outside a practical resolution of a pseudo lens having a numerical aperture larger than that of a projection lens used in the photolithographic process; and updating the initial rendering based on the overhang portion rendering.
摘要翻译：公开了一种用于渲染掩模的方法，系统和计算机程序产品。渲染掩模的方法可以包括：提供用于光刻工艺的初始掩模设计，初始掩模设计包括多边形; 最初在基于像素的图像计算中将初始掩模设计呈现为粗糙掩模表示; 识别突出部分; 并且使用一组子空间渲染悬伸部分，其中来自空间定位的伪像位于具有大于在光刻工艺中使用的投影透镜的数值孔径的假透镜的实际分辨率之外; 并基于突出部分呈现来更新初始呈现。

6. 发明授权

US07536664B2 Physical design system and method 失效
标题翻译：物理设计系统及方法
公开(公告)号：US07536664B2
公开(公告)日：2009-05-19
申请号：US10917193
申请日：2004-08-12
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
摘要翻译：一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。布局单元接收表示网格和字形格式的部分的电路描述。检查单元检查设计的网格和字形部分。精心设计单元从检查的设计生成目标布局。数据准备单元准备掩模制作的目标布局。模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

7. 发明申请

US20090089726A1 Layout Quality Gauge for Integrated Circuit Design 有权
标题翻译：集成电路设计布局质量计
公开(公告)号：US20090089726A1
公开(公告)日：2009-04-02
申请号：US11865252
申请日：2007-10-01
申请人： Fook-Luen Heng , Mark A. Lavin , Jin-Fuw Lee , Thomas Ludwig , Rama Nand Singh , Fanchieh Yee
发明人： Fook-Luen Heng , Mark A. Lavin , Jin-Fuw Lee , Thomas Ludwig , Rama Nand Singh , Fanchieh Yee
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method for layout design includes steps or acts of: receiving a layout for design of an integrated circuit chip; designing mask shapes for the layout; transmitting the mask shapes to a litho simulator for generating wafer shapes; receiving the wafer shapes; calculating electrically equivalent gate lengths for the wafer shapes; analyzing the gate lengths to check for conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate lengths; placing markers on the layout at those locations where the gate length violates the threshold value; and generating a histogram of gate lengths for comparing layouts for electrically equivalent gate lengths for layout quality.
摘要翻译：一种用于布局设计的方法包括以下步骤或动作：接收用于集成电路芯片设计的布局; 设计布局的面具形状; 将掩模形状传送到用于产生晶片形状的光刻模拟器; 接收晶片形状; 计算晶片形状的等效栅极长度; 分析所述栅极长度以检查与阈值的一致性，其中所述阈值表示电等效栅极长度的期望值; 在栅极长度违反阈值的位置放置标记在布局上; 以及生成用于比较用于布局质量的电等效栅极长度的布局的栅极长度的直方图。

8. 发明授权

US07366342B2 Simultaneous computation of multiple points on one or multiple cut lines 有权
标题翻译：在一条或多条切割线上同时计算多个点
公开(公告)号：US07366342B2
公开(公告)日：2008-04-29
申请号：US10694299
申请日：2003-10-27
申请人： Gregg M. Gallatin , Emanuel Gofman , Kafai Lai , Mark A. Lavin , Maharaj Mukherjee , Dov Ramm , Alan E. Rosenbluth , Shlomo Shlafman
发明人： Gregg M. Gallatin , Emanuel Gofman , Kafai Lai , Mark A. Lavin , Maharaj Mukherjee , Dov Ramm , Alan E. Rosenbluth , Shlomo Shlafman
IPC分类号： G06K9/00
CPC分类号： G03F1/36
摘要： Methods, and program storage devices, for performing model-based optical proximity correction by providing a region of interest (ROI) having an interaction distance and locating at least one polygon within the ROI. A cut line of sample points representative of a set of vertices, or plurality of cut lines, are generated within the ROI across at least one lateral edge of the polygon(s). An angular position, and first and second portions of the cut line residing on opposing sides of an intersection between the cut line and the lateral edge of the polygon are determined, followed by generating a new ROI by extending the original ROI beyond its interaction distance based on such angular position, and first and second portions of the cut line. In this manner, a variety of new ROIs may be generated, in a variety of different directions, to ultimately correct for optical proximity.
摘要翻译：方法和程序存储设备，用于通过提供具有交互距离的感兴趣区域（ROI）和定位ROI内的至少一个多边形来执行基于模型的光学邻近度校正。在多边形的至少一个侧边缘上，在ROI内产生代表一组顶点或多个切割线的采样点的切割线。确定角位置，并且切割线的切割线的第一和第二部分位于切割线和多边形的侧边缘之间的交叉点的相对侧上，随后通过将原始ROI延伸超过其相互作用距离来生成新的ROI 在这种角度位置上，以及切割线的第一和第二部分。以这种方式，可以在各种不同的方向上产生各种新的ROI，以最终校正光学邻近度。

9. 发明授权

US07287239B2 Performance in model-based OPC engine utilizing efficient polygon pinning method 有权
标题翻译：在基于模型的OPC引擎中使用高效多边形钉扎方法的性能
公开(公告)号：US07287239B2
公开(公告)日：2007-10-23
申请号：US10694473
申请日：2003-10-27
申请人： Gregg M. Gallatin , Emanuel Gofman , Kafai Lai , Mark A. Lavin , Maharaj Mukherjee , Dov Ramm , Alan E. Rosenbluth , Shlomo Shlafman
发明人： Gregg M. Gallatin , Emanuel Gofman , Kafai Lai , Mark A. Lavin , Maharaj Mukherjee , Dov Ramm , Alan E. Rosenbluth , Shlomo Shlafman
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Methods, and a program storage device for executing such methods, for performing model-based optical proximity correction by providing a mask matrix having a region of interest (ROI) and locating a plurality of points of interest within the mask matrix. A first polygon having a number of vertices representative of the located points of interest is computed, followed by determining a spatial relation between its vertices and the ROI. The vertices of the first polygon are then pinned to boundaries of and within the ROI such that a second polygon is formed on the ROI. The process is repeated for all vertices of the first polygon such that the second polygon is collapsed onto the ROI. This collapsed second polygon is then used to correct for optical proximity.
摘要翻译：方法和用于执行这种方法的程序存储装置，用于通过提供具有感兴趣区域（ROI）的掩模矩阵并且在掩模矩阵内定位多个感兴趣点来执行基于模型的光学邻近校正。计算具有代表所述定位的兴趣点的顶点数的第一多边形，然后确定其顶点和ROI之间的空间关系。然后将第一多边形的顶点固定在ROI的边界和内部，使得在ROI上形成第二多边形。对第一多边形的所有顶点重复该过程，使得第二多边形折叠到ROI上。然后使用这个折叠的第二个多边形来校正光学接近度。

10. 发明授权

US07261981B2 System and method of smoothing mask shapes for improved placement of sub-resolution assist features 失效
标题翻译：平滑掩模形状的系统和方法，以改进子分辨率辅助特征的放置
公开(公告)号：US07261981B2
公开(公告)日：2007-08-28
申请号：US10707778
申请日：2004-01-12
申请人： Mark A. Lavin , Lars W. Liebmann , Scott M. Mansfield , Maharaj Mukherjee , Zengqin Zhao
发明人： Mark A. Lavin , Lars W. Liebmann , Scott M. Mansfield , Maharaj Mukherjee , Zengqin Zhao
IPC分类号： G03F1/00
CPC分类号： G03F1/36
摘要： A method is disclosed for providing associated shapes of an optical lithography mask in relation to predetermined main shapes of the mask. The method includes generating simplified layout patterns from the predetermined main shapes of the mask. Such layout patterns are generated by eliminating detail of the main shapes which leads to unmanufacturable associated shapes while preserving geometrically relevant shape information. The associated shapes are then generated relative to the simplified mask patterns.
摘要翻译：公开了一种相对于掩模的预定主要形状提供光刻掩模的相关形状的方法。该方法包括从掩模的预定主要形状生成简化的布局图案。通过消除导致不可制造的相关形状的主要形状的细节来产生这种布局图案，同时保留几何相关的形状信息。然后相对于简化的掩模图案生成相关联的形状。

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