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1. 发明授权

US08443322B2 Using layout enumeration to facilitate integrated circuit development 失效
标题翻译：使用布局枚举来促进集成电路开发
公开(公告)号：US08443322B2
公开(公告)日：2013-05-14
申请号：US12406996
申请日：2009-03-19
申请人： Philip N. Strenski , Mark A. Lavin
发明人： Philip N. Strenski , Mark A. Lavin
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22
CPC分类号： G06F17/5068
摘要： A method for using layout enumeration to facilitate integrated circuit development includes defining an initial set of design ground rules represented in a notation compatible with a coarse placement grid, for a given layer(s) of an integrated circuit device; defining an initial region of interest for the integrated circuit device; enumerating, according to the initial set of design ground rules, each legal design layout for a given layer of the integrated circuit device in the initial region of interest; running a manufacturing simulation of the enumerated legal design layout data and, responsive to determining one or more failing layouts resulting therefrom, further determining whether the failing layouts may be eliminated by changes in technology parameters and/or updated ground rules. Upon eliminating the one or more failing layouts for the initial region of interest, expanding the initial region of interest and repeating the enumerating, manufacturing simulation, and triage assessment.
摘要翻译：一种用于使用布局枚举以促进集成电路开发的方法包括：为集成电路器件的给定层定义以与粗放置网格兼容的符号表示的设计基准规则的初始集合; 定义集成电路器件的初始感兴趣区域; 列举根据初始设计基准规则，每个法定设计布局为集成电路设备在给定层的初始区域感兴趣; 运行枚举的法律设计布局数据的制造模拟，并且响应于确定由此产生的一个或多个故障布局，进一步确定是否可以通过技术参数和/或更新的基本规则的改变来消除故障布局。在消除初始感兴趣区域的一个或多个失败的布局后，扩展初始的兴趣区域，并重复枚举，制造模拟和分类评估。

2. 发明授权

US06826733B2 Parameter variation tolerant method for circuit design optimization 有权
标题翻译：电路设计优化的参数变化容限方法
公开(公告)号：US06826733B2
公开(公告)日：2004-11-30
申请号：US10159921
申请日：2002-05-30
申请人： David J. Hathaway , Xiaoliang Bai , Chandramouli Visweswariah , Philip N. Strenski
发明人： David J. Hathaway , Xiaoliang Bai , Chandramouli Visweswariah , Philip N. Strenski
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A method for optimizing the design of a chip or system by decreasing the cost function that encompasses a plurality of constraints in the presence of variations in the design parameters is described. The method makes use of numerical optimization, simulated annealing, or any other objective-driven optimization means, and accounts for uncertainties in the modeling of the design variables and functions. A significant reduction in the number of design constraints which are violated at the end of an optimization process is achieved, even when all the design constraints cannot be satisfied. The optimization also reduces the cycle time at which the design operates and limits the increase in the minimum operational cycle time of a particular implementation in the presence of variations that cannot be modeled or unpredictable variations in delay introduced by elements of the design. The method for optimizing the design includes the steps of: defining an objective function computed from variables and functions of the design of the chip or system; deriving a merit function from the objective function by adding to it a plurality of separation terms; and minimizing the merit function which reduces the expected value of the objective function when confronted with significant variations of the design variables and functions.
摘要翻译：描述了通过在存在设计参数的变化的情况下降低包含多个约束的成本函数来优化芯片或系统的设计的方法。该方法利用数值优化，模拟退火或任何其他目标驱动的优化手段，并考虑了设计变量和功能建模中的不确定性。即使在不能满足所有设计限制的情况下，也可以在优化过程结束时，大大减少设计限制的数量。该优化还减少了设计操作的周期时间，并且在存在不能被设计的元件引入的延迟不可模拟或不可预测的变化的变化的情况下限制特定实现的最小操作周期时间的增加。用于优化设计的方法包括以下步骤：定义从芯片或系统的设计的变量和功能计算的目标函数; 通过向目标函数中加入多个分离项，从而得出优点函数; 并且在面对设计变量和功能的显着变化时，最小化功能降低了目标函数的期望值。

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