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1. 发明授权

US07397794B1 Systems and methods for implementing virtual switch planes in a physical switch fabric 有权
标题翻译：在物理交换结构中实现虚拟交换机平面的系统和方法
公开(公告)号：US07397794B1
公开(公告)日：2008-07-08
申请号：US10300639
申请日：2002-11-21
申请人： Philippe Lacroute , Matthew A. Tucker , John D. Weisbloom , Anjan Venkatramani , Jayabharat Boddu , Stefan Dyckerhoff
发明人： Philippe Lacroute , Matthew A. Tucker , John D. Weisbloom , Anjan Venkatramani , Jayabharat Boddu , Stefan Dyckerhoff
IPC分类号： H04L12/50
CPC分类号： H04L49/10 , H04L49/15 , H04L49/1507 , H04L49/30 , H04L49/3027
摘要： A switching device includes multiple interfaces and a switch fabric. The switch fabric includes switch integrated circuits arranged in a number of stages. Multiple virtual switch planes may be implemented in the switch fabric. Data traffic received at the interfaces is selectively assigned to different ones of the virtual switch planes.
摘要翻译：交换设备包括多个接口和交换结构。交换结构包括以多个级布置的开关集成电路。可以在交换结构中实现多个虚拟交换机平面。在接口处接收到的数据流量被选择性地分配给虚拟交换机的不同的平面。

2. 发明授权

US08320369B1 Systems and methods for implementing virtual switch planes in a physical switch fabric 有权
标题翻译：在物理交换结构中实现虚拟交换机平面的系统和方法
公开(公告)号：US08320369B1
公开(公告)日：2012-11-27
申请号：US12134237
申请日：2008-06-06
申请人： Philippe LaCroute , Matthew A Tucker , John D Weisbloom , Anjan Venkatramani , Jayabharat Boddu , Stefan Dyckerhoff
发明人： Philippe LaCroute , Matthew A Tucker , John D Weisbloom , Anjan Venkatramani , Jayabharat Boddu , Stefan Dyckerhoff
IPC分类号： H04Q11/00
CPC分类号： H04L49/10 , H04L49/15 , H04L49/1507 , H04L49/30 , H04L49/3027
摘要： A switching device includes multiple interfaces and a switch fabric. The switch fabric includes switch integrated circuits arranged in a number of stages. Multiple virtual switch planes may be implemented in the switch fabric. Data traffic received at the interfaces is selectively assigned to different ones of the virtual switch planes.
摘要翻译：交换设备包括多个接口和交换结构。交换结构包括以多个级布置的开关集成电路。可以在交换结构中实现多个虚拟交换机平面。在接口处接收到的数据流量被选择性地分配给虚拟交换机的不同的平面。

3. 发明授权

US07787472B2 Hierarchical policers for enforcing differentiated traffic behavior 有权
标题翻译：执行差异化交通行为的分层策略
公开(公告)号：US07787472B2
公开(公告)日：2010-08-31
申请号：US11932104
申请日：2007-10-31
申请人： James Washburn , Spencer Greene , Rami Rahim , Stefan Dyckerhoff , Dennis C. Ferguson , Philippe Lacroute
发明人： James Washburn , Spencer Greene , Rami Rahim , Stefan Dyckerhoff , Dennis C. Ferguson , Philippe Lacroute
IPC分类号： H04L12/28
CPC分类号： H04L47/10 , H04L47/20 , H04L47/2441 , H04L47/32 , H04L47/39
摘要： A hierarchical traffic policer may include a first policer configured to pass first packets when a first condition is met. The first policer also may alter selection information within the passed first packets. A second policer may be configured to pass second packets when a second condition is met. The second policer may be further configured to pass all of the passed first packets from the first policer based on the altered selection information within the passed first packets.
摘要翻译：分级流量监管器可以包括配置成在满足第一条件时传递第一分组的第一策略器。第一个策略器还可以改变所传递的第一个分组内的选择信息。当满足第二条件时，第二策略器可以被配置为传递第二分组。第二策略器可以被进一步配置为基于所传递的第一分组内的改变的选择信息，从第一策略器传递所有传递的第一分组。

4. 发明授权

US07307949B1 Hierarchical policers for enforcing differentiated traffic behavior 有权
标题翻译：执行差异化交通行为的分层策略
公开(公告)号：US07307949B1
公开(公告)日：2007-12-11
申请号：US10298552
申请日：2002-11-19
申请人： James Washburn , Spencer Greene , Rami Rahim , Stefan Dyckerhoff , Dennis C. Ferguson , Philippe Lacroute
发明人： James Washburn , Spencer Greene , Rami Rahim , Stefan Dyckerhoff , Dennis C. Ferguson , Philippe Lacroute
IPC分类号： H04J1/16
CPC分类号： H04L47/10 , H04L47/20 , H04L47/2441 , H04L47/32 , H04L47/39
摘要： A hierarchical traffic policer may include a first policer configured to pass first packets when a first condition is met. The first policer also may alter selection information within the passed first packets. A second policer may be configured to pass second packets when a second condition is met. The second policer may be further configured to pass all of the passed first packets from the first policer based on the altered selection information within the passed first packets.
摘要翻译：分级流量监管器可以包括配置成在满足第一条件时传递第一分组的第一策略器。第一个策略器还可以改变所传递的第一个分组内的选择信息。当满足第二条件时，第二策略器可以被配置为传递第二分组。第二策略器可以被进一步配置为基于所传递的第一分组内的改变的选择信息，从第一策略器传递所有传递的第一分组。

5. 发明授权

US08081654B2 Bandwidth division for packet processing 失效
标题翻译：分组处理带宽划分
公开(公告)号：US08081654B2
公开(公告)日：2011-12-20
申请号：US12723303
申请日：2010-03-12
申请人： Stefan Dyckerhoff , Pankaj Patel , Pradeep Sindhu , Ashok Krishnamurthi , Hann-Hwan Ju , Ramalingam Krishnamurthi Anand
发明人： Stefan Dyckerhoff , Pankaj Patel , Pradeep Sindhu , Ashok Krishnamurthi , Hann-Hwan Ju , Ramalingam Krishnamurthi Anand
IPC分类号： H04J3/16
CPC分类号： H04L45/00 , H04L45/60 , H04L47/125 , H04L49/103 , H04L49/45 , H04L49/552
摘要： A bandwidth divider and method for allocating bandwidth between a plurality of packet processors. The bandwidth divider includes a plurality of counters for measuring the bandwidth of data packets transferred from the bandwidth divider to a respective packet processor; and a controller for analyzing the plurality of counters and transferring a data packet to a selected packet processor based on the contents of the counters. The method monitors the bandwidth consumed by the packet processors; determines, based on the bandwidth consumed by the packet processors, which packet processor has consumed the least amount of bandwidth; and allocates a next data packet to the packet processor which has consumed the least amount of bandwidth.
摘要翻译：一种用于在多个分组处理器之间分配带宽的带宽分配器和方法。带宽分配器包括多个计数器，用于测量从带宽分配器传输到相应分组处理器的数据分组的带宽; 以及用于分析所述多个计数器并基于所述计数器的内容将数据分组传送到所选分组处理器的控制器。该方法监视分组处理器消耗的带宽; 基于分组处理器消耗的带宽来确定哪个分组处理器消耗的带宽最小; 并将下一个数据分组分配给消耗最少带宽的分组处理器。

6. 发明授权

US07706357B1 Bandwidth division for packet processing 有权
标题翻译：分组处理带宽划分
公开(公告)号：US07706357B1
公开(公告)日：2010-04-27
申请号：US11470040
申请日：2006-09-05
申请人： Stefan Dyckerhoff , Pankaj Patel , Pradeep Sindhu , Ashok Krishnamurthi , Hann-Hwan Ju , Ramalingam K. Anand
发明人： Stefan Dyckerhoff , Pankaj Patel , Pradeep Sindhu , Ashok Krishnamurthi , Hann-Hwan Ju , Ramalingam K. Anand
IPC分类号： H04L12/66
CPC分类号： H04L45/00 , H04L45/60 , H04L47/125 , H04L49/103 , H04L49/45 , H04L49/552
摘要： A bandwidth divider and method for allocating bandwidth between a plurality of packet processors. The bandwidth divider includes a plurality of counters for measuring the bandwidth of data packets transferred from the bandwidth divider to a respective packet processor; and a controller for analyzing the plurality of counters and transferring a data packet to a selected packet processor based on the contents of the counters. The method monitors the bandwidth consumed by the packet processors; determines, based on the bandwidth consumed by the packet processors, which packet processor has consumed the least amount of bandwidth; and allocates a next data packet to the packet processor which has consumed the least amount of bandwidth.
摘要翻译：一种用于在多个分组处理器之间分配带宽的带宽分配器和方法。带宽分配器包括多个计数器，用于测量从带宽分配器传输到相应分组处理器的数据分组的带宽; 以及用于分析所述多个计数器并基于所述计数器的内容将数据分组传送到所选分组处理器的控制器。该方法监视分组处理器消耗的带宽; 基于分组处理器消耗的带宽来确定哪个分组处理器消耗的带宽最小; 并将下一个数据分组分配给消耗最少带宽的分组处理器。

7. 发明授权

US07698454B1 Interfacing with streams of differing speeds 有权
标题翻译：接触不同速度的流
公开(公告)号：US07698454B1
公开(公告)日：2010-04-13
申请号：US09991109
申请日：2001-11-26
申请人： Stefan Dyckerhoff , Kong Kritayakirana
发明人： Stefan Dyckerhoff , Kong Kritayakirana
IPC分类号： G06F15/173
CPC分类号： H04L49/254 , H04L47/10 , H04L49/505 , H04L49/9078
摘要： A system processes packet data received in a number of incoming streams of variable speeds. The system includes an input interface, input logic, and one or more packet processors. The input interface receives the packet data and outputs the data using a first arbitration element. The input logic includes flow control logic, a memory, and a dispatch unit. The flow control logic initiates flow control on the data output by the input interface. The memory stores the data from the input interface. The dispatch unit reads the data from the memory using a second arbitration element. The packet processor(s) process the data from the dispatch unit.
摘要翻译：系统处理以多个可变速度的输入流接收的分组数据。该系统包括输入接口，输入逻辑和一个或多个分组处理器。输入接口接收分组数据并使用第一仲裁元素输出数据。输入逻辑包括流控制逻辑，存储器和调度单元。流量控制逻辑启动由输入接口输出的数据的流量控制。存储器存储来自输入接口的数据。调度单元使用第二仲裁元素从存储器读取数据。分组处理器处理来自分派单元的数据。

8. 发明授权

US08131854B2 Interfacing with streams of differing speeds 有权
标题翻译：接触不同速度的流
公开(公告)号：US08131854B2
公开(公告)日：2012-03-06
申请号：US12698794
申请日：2010-02-02
申请人： Stefan Dyckerhoff , Kong Kritayakirana
发明人： Stefan Dyckerhoff , Kong Kritayakirana
IPC分类号： G06F15/173
CPC分类号： H04L49/254 , H04L47/10 , H04L49/505 , H04L49/9078
摘要： A system processes packet data received in a number of incoming streams of variable speeds. The system includes an input interface, input logic, and one or more packet processors. The input interface receives the packet data and outputs the data using a first arbitration element. The input logic includes flow control logic, a memory, and a dispatch unit. The flow control logic initiates flow control on the data output by the input interface. The memory stores the data from the input interface. The dispatch unit reads the data from the memory using a second arbitration element. The packet processor(s) process the data from the dispatch unit.
摘要翻译：系统处理以多个可变速度的输入流接收的分组数据。该系统包括输入接口，输入逻辑和一个或多个分组处理器。输入接口接收分组数据并使用第一仲裁元素输出数据。输入逻辑包括流控制逻辑，存储器和调度单元。流量控制逻辑启动由输入接口输出的数据的流量控制。存储器存储来自输入接口的数据。调度单元使用第二仲裁元素从存储器读取数据。分组处理器处理来自分派单元的数据。

9. 发明申请

US20070220189A1 SYSTEMS AND METHODS FOR PRESERVING THE ORDER OF DATA 有权
标题翻译：保存数据订单的系统和方法
公开(公告)号：US20070220189A1
公开(公告)日：2007-09-20
申请号：US11752620
申请日：2007-05-23
申请人： Raymond Lim , Stefan Dyckerhoff , Jeffrey Libby , Teshager Tesfaye
发明人： Raymond Lim , Stefan Dyckerhoff , Jeffrey Libby , Teshager Tesfaye
IPC分类号： G06F13/00
CPC分类号： G06F13/1626 , G06F9/4881 , G06F12/00 , G06F13/1663 , G06F13/4022 , H04L45/62 , H04L49/90 , H04L49/9094
摘要： A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.
摘要翻译：一种装置包括输入处理单元和输出处理单元。输入处理单元将第一数据分配到一组处理引擎中的一个，将一个处理引擎的标识记录在第一存储器中的位置中，在第二存储器中保留一个或多个对应位置，使得第一数据被处理并且将经处理的第一数据存储在第二存储器中的一个位置中。输出处理单元接收第二数据，将对应于输出存储器中的位置的入口地址分配给第二数据，将第二数据和入口地址传送给一组第二处理引擎，使得第二数据被处理并且将处理的第二数据存储到输出存储器中的位置。

10. 发明授权

US08397233B2 Systems and methods for preserving the order of data 有权
公开(公告)号：US08397233B2
公开(公告)日：2013-03-12
申请号：US11752620
申请日：2007-05-23
申请人： Raymond Marcelino Manese Lim , Stefan Dyckerhoff , Jeffrey Glenn Libby , Teshager Tesfaye
发明人： Raymond Marcelino Manese Lim , Stefan Dyckerhoff , Jeffrey Glenn Libby , Teshager Tesfaye
IPC分类号： G06F9/46 , G06F12/00 , G06F13/00 , G06F9/30 , H04L12/28
CPC分类号： G06F13/1626 , G06F9/4881 , G06F12/00 , G06F13/1663 , G06F13/4022 , H04L45/62 , H04L49/90 , H04L49/9094
摘要： A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.

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