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1. 发明授权

US09673786B2 Flip-flop with reduced retention voltage 有权
公开(公告)号：US09673786B2
公开(公告)日：2017-06-06
申请号：US13862015
申请日：2013-04-12
申请人： QUALCOMM Incorporated
发明人： Seid Hadi Rasouli , Animesh Datta , Jay Madhukar Shah , Martin Saint-Laurent , Peeyush Kumar Parkar , Sachin Bapat , Ramaprasath Vilangudipitchai , Mohamed Hassan Abu-Rahma , Prayag Bhanubhai Patel
IPC分类号： H03K3/02 , H03K3/289 , H03K19/00 , H03K3/012 , H03K3/356 , H03K3/3562
CPC分类号： H03K3/012 , H03K3/356008 , H03K3/35625
摘要： A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

2. 发明授权

US09417643B2 Voltage regulator with variable impedance element 有权
标题翻译：具有可变阻抗元件的电压调节器
公开(公告)号：US09417643B2
公开(公告)日：2016-08-16
申请号：US13842930
申请日：2013-03-15
申请人： QUALCOMM Incorporated
发明人： Martin Saint-Laurent , Yuhe Wang
IPC分类号： G05F1/46 , G05F1/59 , H02M3/157 , G11C5/14 , H02M3/156
CPC分类号： G05F1/468 , G05F1/462 , G05F1/465 , G05F1/59 , G11C5/141 , G11C5/147 , G11C5/148 , H02M3/157 , H02M2003/1566
摘要： A method includes receiving, at a voltage regulator, an activity adjustment signal from a digital circuit. The method also includes controlling one or more variable impedance elements of the voltage regulator to modify an output voltage provided to the digital circuit. The output voltage is based at least in part on the activity adjustment signal.
摘要翻译：一种方法包括在电压调节器处接收来自数字电路的活动调节信号。该方法还包括控制电压调节器的一个或多个可变阻抗元件以修改提供给数字电路的输出电压。输出电压至少部分地基于活动调节信号。

3. 发明申请

US20140266143A1 VOLTAGE REGULATOR 有权
标题翻译：电压稳压器
公开(公告)号：US20140266143A1
公开(公告)日：2014-09-18
申请号：US13842930
申请日：2013-03-15
申请人： QUALCOMM INCORPORATED
发明人： Martin Saint-Laurent , Yuhe Wang
IPC分类号： G05F1/46 , H02M3/157
CPC分类号： G05F1/468 , G05F1/462 , G05F1/465 , G05F1/59 , G11C5/141 , G11C5/147 , G11C5/148 , H02M3/157 , H02M2003/1566
摘要： A method includes receiving, at a voltage regulator, an activity adjustment signal from a digital circuit. The method also includes controlling one or more variable impedance elements of the voltage regulator to modify an output voltage provided to the digital circuit. The output voltage is based at least in part on the activity adjustment signal.
摘要翻译：一种方法包括在电压调节器处接收来自数字电路的活动调节信号。该方法还包括控制电压调节器的一个或多个可变阻抗元件以修改提供给数字电路的输出电压。输出电压至少部分地基于活动调节信号。

4. 发明授权

US10409317B2 Apparatus and methods for reducing clock-ungating induced voltage droop 有权
公开(公告)号：US10409317B2
公开(公告)日：2019-09-10
申请号：US15614358
申请日：2017-06-05
申请人： QUALCOMM Incorporated
发明人： Martin Saint-Laurent , Lam Ho , Carlos Andres Rodriguez Ancer , Bhavin Shah
IPC分类号： G06F17/50 , G06F1/03 , G06F1/3206 , G06F1/3237 , G06F1/324 , G06F1/10 , H03K21/40 , G06F1/08 , H03K19/00 , H03K3/012 , H03K5/131
摘要： Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

5. 发明授权

US09348402B2 Multiple critical paths having different threshold voltages in a single processor core 有权
标题翻译：在单个处理器核心中具有不同阈值电压的多个关键路径
公开(公告)号：US09348402B2
公开(公告)日：2016-05-24
申请号：US13771075
申请日：2013-02-19
申请人： QUALCOMM Incorporated
发明人： Joseph Victor Zanotelli , Martin Saint-Laurent
IPC分类号： G11C16/04 , G06F1/32
CPC分类号： G06F1/3243 , Y02D10/152
摘要： A processor having a multi-Vt critical path is provided that includes both low-Vt devices and high-Vt devices. If the processor is operating in a high performance mode, the multi-Vt critical path is controlled so as to use the low-Vt devices. Conversely, if the processor is operating in a low power mode, the multi-Vt critical path is controlled so as to use the high-Vt devices. In this fashion, the complication of multiple processing cores is avoided in that a single processor core can operate in both the high performance mode and in the low power mode.
摘要翻译：提供具有多Vt关键路径的处理器，其包括低Vt设备和高Vt设备。如果处理器在高性能模式下运行，则会控制多Vt关键路径，以便使用低Vt设备。相反，如果处理器在低功耗模式下工作，则控制多Vt关键路径以便使用高Vt器件。以这种方式，避免了单个处理器核心可以在高性能模式和低功率模式下工作的多处理核心的复杂性。

6. 发明申请

US20140266103A1 DIGITALLY ASSISTED REGULATION FOR AN INTEGRATED CAPLESS LOW-DROPOUT (LDO) VOLTAGE REGULATOR 审中-公开
标题翻译：一体化封装低压差（LDO）电压调节器的数字辅助调节
公开(公告)号：US20140266103A1
公开(公告)日：2014-09-18
申请号：US13843121
申请日：2013-03-15
申请人： QUALCOMM INCORPORATED
发明人： Yuhe Wang , Marzio Pedrali-Noy , Xuhao Huang , Martin Saint-Laurent , Xufeng Chen
IPC分类号： G05F1/46
CPC分类号： G05F1/462 , G05F1/565 , G05F1/575
摘要： Techniques are described that embed a digital assisted regulator with an LDO regulator on a chip without requiring a capacitor external to the chip and to regulate a voltage without undershoot. The digital assisted regulator responds to information regarding operation of the LDO regulator and to a signal that provides advance notification of a load change. When the advance notification signal is received, the digital assisted regulator pulls a circuit's supply voltage up to a chip's incoming supply voltage. When the correct operating voltage has been reached and any undershoot problem removed, the digital assisted regulator balances the current it provides with the current provided by the LDO regulator, to allow a quick response time for other load changes. Also, bandwidth of an LDO regulator may be expanded by use of an advance notice signal to increase bias current of an LDO output device to meet an upcoming load change.
摘要翻译：描述了将芯片上的LDO调节器嵌入数字辅助调节器的技术，而不需要芯片外部的电容器并且调节电压而不会下冲。数字辅助稳压器响应关于LDO调节器的操作的信息以及提供负载变化的提前通知的信号。当接收到提前通知信号时，数字辅助调节器将电路的电源电压提升到芯片的输入电源电压。当达到正确的工作电压并消除任何下冲问题时，数字辅助调节器将其提供的电流与LDO调节器提供的电流平衡，以允许其他负载变化的快速响应时间。此外，LDO调节器的带宽可以通过使用提前通知信号来扩展，以增加LDO输出设备的偏置电流以满足即将到来的负载变化。

7. 发明申请

US20180348809A1 APPARATUS AND METHODS FOR REDUCING CLOCK-UNGATING INDUCED VOLTAGE DROOP 审中-公开
公开(公告)号：US20180348809A1
公开(公告)日：2018-12-06
申请号：US15614358
申请日：2017-06-05
申请人： QUALCOMM Incorporated
发明人： Martin Saint-Laurent , Lam Ho , Carlos Andres Rodriguez Ancer , Bhavin Shah
IPC分类号： G06F1/03 , G06F1/32 , G06F1/10 , H03K21/40
CPC分类号： G06F1/0321 , G06F1/08 , G06F1/10 , G06F1/3206 , G06F1/3237 , G06F1/324 , H03K3/012 , H03K5/131 , H03K19/0016 , H03K21/406
摘要： Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

8. 发明授权

US09785601B2 System and method for reducing cross coupling effects 有权
公开(公告)号：US09785601B2
公开(公告)日：2017-10-10
申请号：US15045282
申请日：2016-02-17
申请人： QUALCOMM Incorporated
发明人： Baker S. Mohammad , Paul D. Bassett , Martin Saint-Laurent
IPC分类号： H03H11/26 , G06F13/40 , H03K3/356 , G06F13/42 , H03K5/15
CPC分类号： G06F13/4077 , G06F13/4072 , G06F13/4291 , H03K3/356069 , H03K3/356113 , H03K5/15 , Y02D10/14 , Y02D10/151
摘要： A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is configured to receive a first input signal and generate a first output signal. The first output signal transitions logic levels after a first delay period when the first input signal transitions from a logic high level to a logic low level. The first output signal transitions logic levels after a second delay period when the first input signal transitions from the logic low level to the logic high level. The first delay element includes a sense amplifier. The first driver circuit is configured to transmit the first output signal over the first bus line. The device also includes a second driver circuit configured to transmit a second output signal over a second bus line.

9. 发明授权

US11347256B2 Apparatus and methods for reducing clock-ungating induced voltage droop 有权
公开(公告)号：US11347256B2
公开(公告)日：2022-05-31
申请号：US17143124
申请日：2021-01-06
申请人： QUALCOMM Incorporated
发明人： Martin Saint-Laurent , Lam Ho , Carlos Andres Rodriguez Ancer , Bhavin Shah
IPC分类号： G06F1/03 , G06F1/3206 , G06F1/3237 , G06F1/324 , G06F1/10 , H03K21/40 , G06F1/08 , H03K19/00 , H03K3/012 , H03K5/131
摘要： Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

10. 发明授权

US11047946B2 Differential current sensing with robust path, voltage offset removal and process, voltage, temperature (PVT) tolerance 有权
公开(公告)号：US11047946B2
公开(公告)日：2021-06-29
申请号：US15974271
申请日：2018-05-08
申请人： QUALCOMM Incorporated
发明人： Nam Dang , Rajeev Jain , Swarna Navubothu , Alan Lewis , Martin Saint-Laurent , Tung Nang Pham , Joseph Terregrossa , Paras Gupta , Somasekhar Maradani
IPC分类号： G01R35/00 , G01R19/25 , H03K5/003
摘要： Aspects of the disclosure are directed to voltage-based current sensing. In accordance with one aspect, voltage-based current sensing may include performing a coarse calibration of a voltage based current sensor to determine a coarse offset; performing a fine calibration of the voltage based current sensor to determine a fine offset; performing a frequency calibration of the voltage based current sensor to determine a frequency offset; and performing a transfer function calibration of the voltage based current sensor to determine a sensor transfer function using one or more of the coarse offset, the fine offset and the frequency offset; and measuring a load current using the sensor transfer function.

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