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1. 发明申请

US20060265676A1 Method and apparatus for verifying specification, and computer product 有权
标题翻译：用于验证规格的方法和装置以及计算机产品
公开(公告)号：US20060265676A1
公开(公告)日：2006-11-23
申请号：US11214848
申请日：2005-08-31
申请人： Qiang Zhu , Ryosuke Oishi , Tsuneo Nakata
发明人： Qiang Zhu , Ryosuke Oishi , Tsuneo Nakata
IPC分类号： G06F17/50 , G06F9/44
CPC分类号： G06F8/10 , G06Q20/4012
摘要： An apparatus for verifying a specification includes a use-case extracting unit, a first setting unit, an operation extracting unit, a second setting unit, and a determining unit. The use-case extracting unit extracts an unprocessed use case from specification data. The first setting unit sets a condition based on a precondition, a postcondition, and an invariant condition for the use case. The operation extracting unit selects an event flow of an unprocessed path from the specification data and extracts an unprocessed operation (description) from the event flow selected. The second setting unit sets a precondition and a postcondition for the operation based on the extracted operation (description). The determining unit determines whether the invariant condition is valid.
摘要翻译：用于验证规范的装置包括用例提取单元，第一设置单元，操作提取单元，第二设置单元和确定单元。用例提取单元从规范数据中提取未处理的用例。第一设置单元基于用例的前提条件，后置条件和不变条件设置条件。操作提取单元从指定数据中选择未处理路径的事件流，并从所选择的事件流中提取未处理的操作（描述）。第二设定单元基于提取的操作（描述）设置操作的前提条件和后置条件。确定单元确定不变条件是否有效。

2. 发明授权

US07937680B2 Method and apparatus for verifying specification, and computer product 有权
标题翻译：用于验证规格的方法和装置以及计算机产品
公开(公告)号：US07937680B2
公开(公告)日：2011-05-03
申请号：US11214848
申请日：2005-08-31
申请人： Qiang Zhu , Ryosuke Oishi , Tsuneo Nakata , Takashi Hasegawa
发明人： Qiang Zhu , Ryosuke Oishi , Tsuneo Nakata , Takashi Hasegawa
IPC分类号： G06F17/50 , G06F21/00 , G06Q20/00
CPC分类号： G06F8/10 , G06Q20/4012
摘要： An apparatus for verifying a specification includes a use-case extracting unit, a first setting unit, an operation extracting unit, a second setting unit, and a determining unit. The use-case extracting unit extracts an unprocessed use case from specification data. The first setting unit sets a condition based on a precondition, a postcondition, and an invariant condition for the use case. The operation extracting unit selects an event flow of an unprocessed path from the specification data and extracts an unprocessed operation (description) from the event flow selected. The second setting unit sets a precondition and a postcondition for the operation based on the extracted operation (description). The determining unit determines whether the invariant condition is valid.
摘要翻译：用于验证规范的装置包括用例提取单元，第一设置单元，操作提取单元，第二设置单元和确定单元。用例提取单元从规范数据中提取未处理的用例。第一设置单元基于用例的前提条件，后置条件和不变条件设置条件。操作提取单元从指定数据中选择未处理路径的事件流，并从所选择的事件流中提取未处理的操作（描述）。第二设定单元基于提取的操作（描述）设置操作的前提条件和后置条件。确定单元确定不变条件是否有效。

3. 发明授权

US07984403B2 Verification supporting system 有权
标题翻译：验证支持系统
公开(公告)号：US07984403B2
公开(公告)日：2011-07-19
申请号：US12359105
申请日：2009-01-23
申请人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
发明人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.
摘要翻译：从验证目标电路的配置指定要验证的验证目标寄存器，并且提取需要验证的模式作为关于指定验证目标寄存器的覆盖标准。当提取模式时，准备一个DIRW矩阵，以指示包含在验证目标电路中的寄存器中的四个状态中声明，初始化，读取和写入中的可能发生的状态转换，并用于确定两个覆盖标准，矩阵覆盖标准和实施覆盖标准。

4. 发明申请

US20090276740A1 VERIFICATION SUPPORTING APPARATUS, VERIFICATION SUPPORTING METHOD, AND COMPUTER PRODUCT 有权
标题翻译：验证支持设备，验证支持方法和计算机产品
公开(公告)号：US20090276740A1
公开(公告)日：2009-11-05
申请号：US12335105
申请日：2008-12-15
申请人： Akio Matsuda , Ryosuke Oishi , Koichiro Takayama , Tsuneo Nakata , Rafael Kazumiti Morizawa
发明人： Akio Matsuda , Ryosuke Oishi , Koichiro Takayama , Tsuneo Nakata , Rafael Kazumiti Morizawa
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output.
摘要翻译：在验证支持装置中，记录单元记录其中可能发生在待验证电路的寄存器中可能发生的状态转换的DIRW矩阵和关于与状态转换相对应的路径的有效性的信息，并且获取单元获取控制数据流图包括其中写入数据流图的控制流图。当指定用于验证的寄存器时，从控制数据流程图中提取其中描述的指定寄存器的数据流图。从提取的数据流图中，提取指示关于寄存器的数据流的路径。识别提取的路径的状态转换，并且如果在DIRW矩阵中设置状态转换，则将与DIRW矩阵和路径中设置的有效性有关的信息相关并输出。

5. 发明授权

US08312400B2 Verification supporting system 有权
标题翻译：验证支持系统
公开(公告)号：US08312400B2
公开(公告)日：2012-11-13
申请号：US13157534
申请日：2011-06-10
申请人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
发明人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.
摘要翻译：从验证目标电路的配置指定要验证的验证目标寄存器，并且提取需要验证的模式作为关于指定验证目标寄存器的覆盖标准。当提取模式时，准备一个DIRW矩阵，以指示包含在验证目标电路中的寄存器中的四个状态中声明，初始化，读取和写入中的可能发生的状态转换，并用于确定两个覆盖标准，矩阵覆盖标准和实施覆盖标准。

6. 发明申请

US20110239172A1 VERIFICATION SUPPORTING SYSTEM 有权
标题翻译：验证支持系统
公开(公告)号：US20110239172A1
公开(公告)日：2011-09-29
申请号：US13157534
申请日：2011-06-10
申请人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
发明人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.
摘要翻译：从验证目标电路的配置指定要验证的验证目标寄存器，并且提取需要验证的模式作为关于指定验证目标寄存器的覆盖标准。当提取模式时，准备一个DIRW矩阵，以指示包含在验证目标电路中的寄存器中的四个状态中声明，初始化，读取和写入中的可能发生的状态转换，并用于确定两个覆盖标准，矩阵覆盖标准和实施覆盖标准。

7. 发明授权

US08015519B2 Verification supporting apparatus, verification supporting method, and computer product 有权
标题翻译：验证支持设备，验证支持方式和计算机产品
公开(公告)号：US08015519B2
公开(公告)日：2011-09-06
申请号：US12335105
申请日：2008-12-15
申请人： Akio Matsuda , Ryosuke Oishi , Koichiro Takayama , Tsuneo Nakata , Rafael Kazumiti Morizawa
发明人： Akio Matsuda , Ryosuke Oishi , Koichiro Takayama , Tsuneo Nakata , Rafael Kazumiti Morizawa
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output.
摘要翻译：在验证支持装置中，记录单元记录其中可能发生在待验证电路的寄存器中可能发生的状态转换的DIRW矩阵和关于与状态转换相对应的路径的有效性的信息，并且获取单元获取控制数据流图包括其中写入数据流图的控制流图。当指定用于验证的寄存器时，从控制数据流程图中提取其中描述的指定寄存器的数据流图。从提取的数据流图中，提取指示关于寄存器的数据流的路径。识别提取的路径的状态转换，并且如果在DIRW矩阵中设置状态转换，则将与DIRW矩阵和路径中设置的有效性有关的信息相关并输出。

8. 发明申请

US20090287965A1 VERIFICATION SUPPORTING SYSTEM 有权
标题翻译：验证支持系统
公开(公告)号：US20090287965A1
公开(公告)日：2009-11-19
申请号：US12359105
申请日：2009-01-23
申请人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
发明人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06F11/34
CPC分类号： G06F17/5022 , G06F17/504
摘要： A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.
摘要翻译：从验证对象电路的配置指定要验证的验证目标寄存器，并且提取需要验证的模式作为关于指定的验证目标寄存器的覆盖标准。当提取模式时，准备一个DIRW矩阵，以指示包含在验证目标电路中的寄存器中的四个状态中声明，初始化，读取和写入中的可能发生的状态转换，并用于确定两个覆盖标准，矩阵覆盖标准和实施覆盖标准。

9. 发明申请

US20080312890A1 SPECIFICATION VERIFICATION PROGRAM, COMPUTER-READABLE STORAGE MEDIUM STORING SPECIFICATION VERIFICATION PROGRAM, SPECIFICATION VERIFICATION APPARATUS, AND SPECIFICATION VERIFICATION METHOD 有权
标题翻译：规格验证程序，计算机可读存储介质存储规范验证程序，规范验证设备和规范验证方法
公开(公告)号：US20080312890A1
公开(公告)日：2008-12-18
申请号：US12136378
申请日：2008-06-10
申请人： Qiang ZHU , Hiroaki Iwashita , Koichiro Takayama , Tsuneo Nakata
发明人： Qiang ZHU , Hiroaki Iwashita , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06G7/48
CPC分类号： G06F8/10
摘要： Conditions necessary to be satisfied for execution of each use case from a use case description indicative of a requirements specification of the design object are acquired. Then a state satisfying the conditions, from among a set of states represented in a finite state machine model indicative of a design specification of the design object are detected. A presence or absence of an undetected state in the set of states in accordance with the detection is determined and output.
摘要翻译：获取从指示设计对象的要求规范的用例描述中执行每个用例所需要的条件。然后，检测从表示设计对象的设计规格的有限状态机模型中表示的一组状态中满足条件的状态。确定并输出根据检测的状态集合中的未检测状态的存在或不存在。

10. 发明授权

US07752576B2 Design support apparatus, design support method, and computer product for designing function module from specification description 失效
标题翻译：设计支持设备，设计支持方法和计算机产品，用于从规范描述中设计功能模块
公开(公告)号：US07752576B2
公开(公告)日：2010-07-06
申请号：US11394390
申请日：2006-03-31
申请人： Qiang Zhu , Tsuneo Nakata
发明人： Qiang Zhu , Tsuneo Nakata
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5045
摘要： An input unit inputs specification description that includes a plurality of pieces of processing information each indicative of a processing performed by a design object and association information indicative of associations among the processing information. A node generating unit generates a node for each of the processing information. A link generating unit generates, based on the association information, a link that couples nodes generated by the node generating unit. A sub-chart generating unit configured to generate a plurality of sub-charts by dividing a chart indicating a content of the specification description, based on the node and the link. A function-module generating unit generates, for each of the sub-charts, a function module that executes a function based on the processing information corresponding to the node in the sub-chart and the association information corresponding to the link in the sub-chart.
摘要翻译：输入单元输入包括指示由设计对象执行的处理的多个处理信息和指示处理信息之间的关联的关联信息的规范描述。节点生成单元为每个处理信息生成节点。链接生成单元基于关联信息生成将由节点生成单元生成的节点进行耦合的链接。子图生成部，其基于所述节点和所述链接，分割表示所述规格说明的内容的图来生成多个子图。功能模块生成单元针对每个子图生成基于与子图中的节点对应的处理信息和与子图中的链接对应的关联信息执行功能的功能模块。

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