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1. 发明授权

US3654441A Four-phase high speed counter 失效
标题翻译：四相高速计数器
公开(公告)号：US3654441A
公开(公告)日：1972-04-04
申请号：US3654441D
申请日：1970-11-16
申请人： RCA CORP
发明人： BHARALI UIPALANANDA
IPC分类号： H03K23/00 , G06M1/14 , H03K23/08
CPC分类号： H03K23/001
摘要： In response to each pulse to be counted, the bit stored in each stage of the counter is sensed. In the case of up-counting, when the j least significant bits are 1 and the j + 1th least significant bit is a 0, the stages storing these j + 1 bits are caused concurrently to change state, and where j is any integer which is less than n, and n is the number of stages in the counter. In the case of down-counting, the same procedure is followed for the complementary case. The counter may be implemented with metal oxide semiconductor (MOS) field-effect transistors.
摘要翻译：响应于要计数的每个脉冲，感测存储在计数器的每个级中的位。在递增计数的情况下，当j个最低有效位为1并且j + 1个最低有效位为0时，存储这些j + 1位的级同时引起改变状态，并且其中j是任何整数，小于n，n是计数器中的级数。在下计数的情况下，补充案件遵循相同的程序。计数器可以用金属氧化物半导体（MOS）场效应晶体管来实现。

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